diff options
| author | Christian Konig <christian.koenig@amd.com> | 2013-02-21 15:16:53 +0000 |
|---|---|---|
| committer | Christian Konig <christian.koenig@amd.com> | 2013-02-21 15:16:53 +0000 |
| commit | a38ccb4b32fca60264b734090a00cb850bcfbaf7 (patch) | |
| tree | 3b32e218f24810f5170af71a1e502995945596f8 /lib | |
| parent | 7fa9957b16ee314b294da8abbec70bd2f1dfa608 (diff) | |
R600/SI: rework VOP1_* patterns v2
Fixing asm operation names.
v2: use ZERO constant, also add asm operands
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175748 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/R600/SIInstrInfo.td | 38 |
1 files changed, 21 insertions, 17 deletions
diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td index 8b90d45645..2b313079da 100644 --- a/lib/Target/R600/SIInstrInfo.td +++ b/lib/Target/R600/SIInstrInfo.td @@ -141,29 +141,33 @@ class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 < opName, pattern >; -class VOP1_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc, - string opName, list<dag> pattern> : - VOP1 < - op, (outs vrc:$dst), (ins arc:$src0), opName, pattern - >; +multiclass VOP1_Helper <bits<8> op, RegisterClass drc, RegisterClass src, + string opName, list<dag> pattern> { -multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern> { - def _e32: VOP1_Helper <op, VReg_32, VSrc_32, opName, pattern>; - def _e64 : VOP3_32 <{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, - opName, [] + def _e32: VOP1 < + op, (outs drc:$dst), (ins src:$src0), + opName#"_e32 $dst, $src0", pattern >; -} -multiclass VOP1_64 <bits<8> op, string opName, list<dag> pattern> { - - def _e32 : VOP1_Helper <op, VReg_64, VSrc_64, opName, pattern>; - - def _e64 : VOP3_64 < + def _e64 : VOP3 < {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, - opName, [] - >; + (outs drc:$dst), + (ins src:$src0, + i32imm:$abs, i32imm:$clamp, + i32imm:$omod, i32imm:$neg), + opName#"_e64 $dst, $src0, $abs, $clamp, $omod, $neg", [] + > { + let SRC1 = SIOperand.ZERO; + let SRC2 = SIOperand.ZERO; + } } +multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern> + : VOP1_Helper <op, VReg_32, VSrc_32, opName, pattern>; + +multiclass VOP1_64 <bits<8> op, string opName, list<dag> pattern> + : VOP1_Helper <op, VReg_64, VSrc_64, opName, pattern>; + class VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc, string opName, list<dag> pattern> : VOP2 < |