Instead of passing in an unsigned value for the optimization level, use an enum,

which better identifies what the optimization is doing. And is more flexible for
future uses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70440 91177308-0d34-0410-b5e6-96231b3b80d8

68 files changed, 285 insertions, 196 deletions

diff --git a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index e0a526c372..319bbdbe65 100644
--- a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -27,7 +27,6 @@
 #include "llvm/Target/TargetAsmInfo.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/ADT/SmallPtrSet.h"
@@ -42,7 +41,7 @@ AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
 
 char AsmPrinter::ID = 0;
 AsmPrinter::AsmPrinter(raw_ostream &o, TargetMachine &tm,
-                       const TargetAsmInfo *T, unsigned OL, bool VDef)
+                       const TargetAsmInfo *T, CodeGenOpt::Level OL, bool VDef)
   : MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL), O(o),
     TM(tm), TAI(T), TRI(tm.getRegisterInfo()),
     IsInTextSection(false)
diff --git a/lib/CodeGen/AsmPrinter/DwarfWriter.cpp b/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
index 5d6a70f622..499f800d7e 100644
--- a/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
+++ b/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
@@ -3351,7 +3351,7 @@ public:
   }
 
   /// ValidDebugInfo - Return true if V represents valid debug info value.
-  bool ValidDebugInfo(Value *V, unsigned OptLevel) {
+  bool ValidDebugInfo(Value *V, CodeGenOpt::Level OptLevel) {
     if (!V)
       return false;
 
@@ -3393,7 +3393,7 @@ public:
     case DW_TAG_lexical_block:
       /// FIXME. This interfers with the qualitfy of generated code when 
       /// during optimization.
-      if (OptLevel != 0)
+      if (OptLevel != CodeGenOpt::None)
         return false;
     default:
       break;
@@ -4731,7 +4731,7 @@ void DwarfWriter::EndFunction(MachineFunction *MF) {
 }
 
 /// ValidDebugInfo - Return true if V represents valid debug info value.
-bool DwarfWriter::ValidDebugInfo(Value *V, unsigned OptLevel) {
+bool DwarfWriter::ValidDebugInfo(Value *V, CodeGenOpt::Level OptLevel) {
   return DD && DD->ValidDebugInfo(V, OptLevel);
 }
 
diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp
index 92aeb64c7d..faaa41b68b 100644
--- a/lib/CodeGen/LLVMTargetMachine.cpp
+++ b/lib/CodeGen/LLVMTargetMachine.cpp
@@ -55,7 +55,7 @@ FileModel::Model
 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
                                        raw_ostream &Out,
                                        CodeGenFileType FileType,
-                                       unsigned OptLevel) {
+                                       CodeGenOpt::Level OptLevel) {
   // Add common CodeGen passes.
   if (addCommonCodeGenPasses(PM, OptLevel))
     return FileModel::Error;
@@ -69,7 +69,7 @@ LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
   if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  if (OptLevel != 0)
+  if (OptLevel != CodeGenOpt::None)
     PM.add(createLoopAlignerPass());
 
   switch (FileType) {
@@ -94,7 +94,7 @@ LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
 /// finish up adding passes to emit the file, if necessary.
 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
                                                   MachineCodeEmitter *MCE,
-                                                  unsigned OptLevel) {
+                                                  CodeGenOpt::Level OptLevel) {
   if (MCE)
     addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
 
@@ -114,7 +114,7 @@ bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
 ///
 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
                                                    MachineCodeEmitter &MCE,
-                                                   unsigned OptLevel) {
+                                                   CodeGenOpt::Level OptLevel) {
   // Add common CodeGen passes.
   if (addCommonCodeGenPasses(PM, OptLevel))
     return true;
@@ -132,15 +132,15 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
   return false; // success!
 }
 
-/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
-/// both emitting to assembly files or machine code output.
+/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
+/// emitting to assembly files or machine code output.
 ///
 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
-                                               unsigned OptLevel) {
+                                               CodeGenOpt::Level OptLevel) {
   // Standard LLVM-Level Passes.
 
   // Run loop strength reduction before anything else.
-  if (OptLevel != 0) {
+  if (OptLevel != CodeGenOpt::None) {
     PM.add(createLoopStrengthReducePass(getTargetLowering()));
     if (PrintLSR)
       PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
@@ -154,7 +154,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 
-  if (OptLevel != 0)
+  if (OptLevel != CodeGenOpt::None)
     PM.add(createCodeGenPreparePass(getTargetLowering()));
 
   PM.add(createStackProtectorPass(getTargetLowering()));
@@ -168,7 +168,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
 
   // Enable FastISel with -fast, but allow that to be overridden.
   if (EnableFastISelOption == cl::BOU_TRUE ||
-      (OptLevel == 0 && EnableFastISelOption != cl::BOU_FALSE))
+      (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
     EnableFastISel = true;
 
   // Ask the target for an isel.
@@ -179,7 +179,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
   if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  if (OptLevel != 0) {
+  if (OptLevel != CodeGenOpt::None) {
     PM.add(createMachineLICMPass());
     PM.add(createMachineSinkingPass());
   }
@@ -192,7 +192,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
   PM.add(createRegisterAllocator());
 
   // Perform stack slot coloring.
-  if (OptLevel != 0)
+  if (OptLevel != CodeGenOpt::None)
     PM.add(createStackSlotColoringPass());
 
   if (PrintMachineCode)  // Print the register-allocated code
@@ -217,7 +217,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
     PM.add(createMachineFunctionPrinterPass(cerr));
 
   // Second pass scheduler.
-  if (OptLevel != 0 && !DisablePostRAScheduler) {
+  if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
     PM.add(createPostRAScheduler());
 
     if (PrintMachineCode)
@@ -225,7 +225,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
   }
 
   // Branch folding must be run after regalloc and prolog/epilog insertion.
-  if (OptLevel != 0)
+  if (OptLevel != CodeGenOpt::None)
     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
 
   if (PrintMachineCode)
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 226699b672..1378f25387 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -57,7 +57,7 @@ namespace {
     SelectionDAG &DAG;
     const TargetLowering &TLI;
     CombineLevel Level;
-    unsigned OptLevel;
+    CodeGenOpt::Level OptLevel;
     bool LegalOperations;
     bool LegalTypes;
 
@@ -254,7 +254,7 @@ namespace {
     }
 
 public:
-    DAGCombiner(SelectionDAG &D, AliasAnalysis &A, unsigned OL)
+    DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
       : DAG(D),
         TLI(D.getTargetLoweringInfo()),
         Level(Unrestricted),
@@ -4784,7 +4784,7 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) {
   SDValue Ptr   = LD->getBasePtr();
 
   // Try to infer better alignment information than the load already has.
-  if (OptLevel != 0 && LD->isUnindexed()) {
+  if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
     if (unsigned Align = InferAlignment(Ptr, DAG)) {
       if (Align > LD->getAlignment())
         return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
@@ -4904,7 +4904,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
   SDValue Ptr   = ST->getBasePtr();
 
   // Try to infer better alignment information than the store already has.
-  if (OptLevel != 0 && ST->isUnindexed()) {
+  if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
     if (unsigned Align = InferAlignment(Ptr, DAG)) {
       if (Align > ST->getAlignment())
         return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
@@ -6093,7 +6093,7 @@ SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
 // SelectionDAG::Combine - This is the entry point for the file.
 //
 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
-                           unsigned OptLevel) {
+                           CodeGenOpt::Level OptLevel) {
   /// run - This is the main entry point to this class.
   ///
   DAGCombiner(*this, AA, OptLevel).Run(Level);
diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index a7801ebccf..09ac586dd5 100644
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -327,7 +327,7 @@ bool FastISel::SelectCall(User *I) {
   default: break;
   case Intrinsic::dbg_stoppoint: {
     DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
-    if (DW && DW->ValidDebugInfo(SPI->getContext(), 0)) {
+    if (DW && DW->ValidDebugInfo(SPI->getContext(), CodeGenOpt::None)) {
       DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
       std::string Dir, FN;
       unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
@@ -344,7 +344,7 @@ bool FastISel::SelectCall(User *I) {
   }
   case Intrinsic::dbg_region_start: {
     DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
-    if (DW && DW->ValidDebugInfo(RSI->getContext(), 0)) {
+    if (DW && DW->ValidDebugInfo(RSI->getContext(), CodeGenOpt::None)) {
       unsigned ID = 
         DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext()));
       const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
@@ -354,7 +354,7 @@ bool FastISel::SelectCall(User *I) {
   }
   case Intrinsic::dbg_region_end: {
     DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
-    if (DW && DW->ValidDebugInfo(REI->getContext(), 0)) {
+    if (DW && DW->ValidDebugInfo(REI->getContext(), CodeGenOpt::None)) {
      unsigned ID = 0;
      DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext()));
      if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) {
@@ -380,7 +380,7 @@ bool FastISel::SelectCall(User *I) {
     DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
     Value *SP = FSI->getSubprogram();
 
-    if (DW->ValidDebugInfo(SP, 0)) {
+    if (DW->ValidDebugInfo(SP, CodeGenOpt::None)) {
       // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
       // (most?) gdb expects.
       DebugLoc PrevLoc = DL;
@@ -425,7 +425,7 @@ bool FastISel::SelectCall(User *I) {
   case Intrinsic::dbg_declare: {
     DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
     Value *Variable = DI->getVariable();
-    if (DW && DW->ValidDebugInfo(Variable, 0)) {
+    if (DW && DW->ValidDebugInfo(Variable, CodeGenOpt::None)) {
       // Determine the address of the declared object.
       Value *Address = DI->getAddress();
       if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index efa62be36d..9c43065040 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -55,7 +55,7 @@ namespace {
 class VISIBILITY_HIDDEN SelectionDAGLegalize {
   TargetLowering &TLI;
   SelectionDAG &DAG;
-  unsigned OptLevel;
+  CodeGenOpt::Level OptLevel;
   bool TypesNeedLegalizing;
 
   // Libcall insertion helpers.
@@ -139,7 +139,7 @@ class VISIBILITY_HIDDEN SelectionDAGLegalize {
 
 public:
   explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing,
-                                unsigned ol);
+                                CodeGenOpt::Level ol);
 
   /// getTypeAction - Return how we should legalize values of this type, either
   /// it is already legal or we need to expand it into multiple registers of
@@ -350,7 +350,7 @@ SelectionDAGLegalize::ShuffleWithNarrowerEltType(MVT NVT, MVT VT,  DebugLoc dl,
 }
 
 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
-                                           bool types, unsigned ol)
+                                           bool types, CodeGenOpt::Level ol)
   : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
     TypesNeedLegalizing(types), ValueTypeActions(TLI.getValueTypeActions()) {
   assert(MVT::LAST_VALUETYPE <= 32 &&
@@ -1276,7 +1276,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
         unsigned Line = DSP->getLine();
         unsigned Col = DSP->getColumn();
 
-        if (OptLevel == 0) {
+        if (OptLevel == CodeGenOpt::None) {
           // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
           // won't hurt anything.
           if (useDEBUG_LOC) {
@@ -8571,7 +8571,8 @@ SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
 
 // SelectionDAG::Legalize - This is the entry point for the file.
 //
-void SelectionDAG::Legalize(bool TypesNeedLegalizing, unsigned OptLevel) {
+void SelectionDAG::Legalize(bool TypesNeedLegalizing,
+                            CodeGenOpt::Level OptLevel) {
   /// run - This is the main entry point to this class.
   ///
   SelectionDAGLegalize(*this, TypesNeedLegalizing, OptLevel).LegalizeDAG();
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
index c87820a97b..af73b28fae 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
@@ -630,6 +630,6 @@ void ScheduleDAGFast::ListScheduleBottomUp() {
 //===----------------------------------------------------------------------===//
 
 llvm::ScheduleDAGSDNodes *
-llvm::createFastDAGScheduler(SelectionDAGISel *IS, unsigned) {
+llvm::createFastDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
   return new ScheduleDAGFast(*IS->MF);
 }
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
index 2ac934a0d0..c432534999 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
@@ -261,7 +261,7 @@ void ScheduleDAGList::ListScheduleTopDown() {
 /// new hazard recognizer. This scheduler takes ownership of the hazard
 /// recognizer and deletes it when done.
 ScheduleDAGSDNodes *
-llvm::createTDListDAGScheduler(SelectionDAGISel *IS, unsigned) {
+llvm::createTDListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
   return new ScheduleDAGList(*IS->MF,
                              new LatencyPriorityQueue(),
                              IS->CreateTargetHazardRecognizer());
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index aecd02aba3..c97e2a8c86 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1505,7 +1505,7 @@ bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
 //===----------------------------------------------------------------------===//
 
 llvm::ScheduleDAGSDNodes *
-llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
+llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
   const TargetMachine &TM = IS->TM;
   const TargetInstrInfo *TII = TM.getInstrInfo();
   const TargetRegisterInfo *TRI = TM.getRegisterInfo();
@@ -1519,7 +1519,7 @@ llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
 }
 
 llvm::ScheduleDAGSDNodes *
-llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
+llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
   const TargetMachine &TM = IS->TM;
   const TargetInstrInfo *TII = TM.getInstrInfo();
   const TargetRegisterInfo *TRI = TM.getRegisterInfo();
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index afadd62caa..01d73b3ffb 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -45,7 +45,6 @@
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetIntrinsicInfo.h"
 #include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/CommandLine.h"
@@ -335,7 +334,8 @@ void FunctionLoweringInfo::set(Function &fn, MachineFunction