diff options
| author | Dan Gohman <gohman@apple.com> | 2009-10-09 22:09:05 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2009-10-09 22:09:05 +0000 |
| commit | 769b7f89534caed11d7595b5c84aa47d3de30ad9 (patch) | |
| tree | dfdcd037b8c9dc6e069f007a9e114c555c159b22 /lib | |
| parent | bdb984bc2757114bc706026603ed40d7f508c4c1 (diff) | |
Add a const qualifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83677 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/TargetRegisterInfo.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/TargetRegisterInfo.cpp b/lib/Target/TargetRegisterInfo.cpp index 43123991ea..fac67e2e1a 100644 --- a/lib/Target/TargetRegisterInfo.cpp +++ b/lib/Target/TargetRegisterInfo.cpp @@ -62,14 +62,14 @@ TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, EVT VT) const { /// getAllocatableSetForRC - Toggle the bits that represent allocatable /// registers for the specific register class. -static void getAllocatableSetForRC(MachineFunction &MF, +static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R){ for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), E = RC->allocation_order_end(MF); I != E; ++I) R.set(*I); } -BitVector TargetRegisterInfo::getAllocatableSet(MachineFunction &MF, +BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC) const { BitVector Allocatable(NumRegs); if (RC) { |