diff options
| author | Owen Anderson <resistor@mac.com> | 2010-10-21 03:11:16 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2010-10-21 03:11:16 +0000 |
| commit | d9707e3d852622197133a73dcb788a7fcd364015 (patch) | |
| tree | faca0499ec6e582d1aa18f7c43292fa665669f48 /lib | |
| parent | 13a949071ce2c887ae81db9f6880a660ff33a76d (diff) | |
Revert r116983, which is breaking all the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116987 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA8.td | 22 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA9.td | 8 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMScheduleV6.td | 12 |
3 files changed, 4 insertions, 38 deletions
diff --git a/lib/Target/ARM/ARMScheduleA8.td b/lib/Target/ARM/ARMScheduleA8.td index 32d9d66837..7573182434 100644 --- a/lib/Target/ARM/ARMScheduleA8.td +++ b/lib/Target/ARM/ARMScheduleA8.td @@ -331,28 +331,6 @@ def CortexA8Itineraries : ProcessorItineraries< InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<29, [A8_NPipe], 0>, InstrStage<29, [A8_NLSPipe]>], [29, 1]>, - - // - // Integer to Single-precision Move - InstrItinData<IIC_fpMOVIS, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<1, [A8_NPipe]>], - [2, 1]>, - // - // Integer to Double-precision Move - InstrItinData<IIC_fpMOVID, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<1, [A8_NPipe]>], - [2, 1, 1]>, - // - // Single-precision to Integer Move - InstrItinData<IIC_fpMOVSI, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<1, [A8_NPipe]>], - [20, 1]>, - // - // Double-precision to Integer Move - InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<1, [A8_NPipe]>], - [20, 20, 1]>, - // // Single-precision FP Load InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td index 548bc7cd60..c22367716c 100644 --- a/lib/Target/ARM/ARMScheduleA9.td +++ b/lib/Target/ARM/ARMScheduleA9.td @@ -641,7 +641,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, InstrStage<1, [A9_NPipe]>], - [2, 1]>, + [1, 1]>, // // Double-precision to Integer Move InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, @@ -649,7 +649,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, InstrStage<1, [A9_NPipe]>], - [2, 1, 1]>, + [1, 1, 1]>, // // Single-precision FP Load InstrItinData<IIC_fpLoad32, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, @@ -1430,7 +1430,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, InstrStage<1, [A9_NPipe]>], - [1, 1]>, + [2, 1]>, // // Integer to Double-precision Move InstrItinData<IIC_VMOVID , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, @@ -1438,7 +1438,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, InstrStage<1, [A9_NPipe]>], - [1, 1, 1]>, + [2, 1, 1]>, // // Single-precision to Integer Move InstrItinData<IIC_VMOVSI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, diff --git a/lib/Target/ARM/ARMScheduleV6.td b/lib/Target/ARM/ARMScheduleV6.td index e4e9c13bd9..b845130e37 100644 --- a/lib/Target/ARM/ARMScheduleV6.td +++ b/lib/Target/ARM/ARMScheduleV6.td @@ -247,18 +247,6 @@ def ARMV6Itineraries : ProcessorItineraries< // Double-precision FP SQRT InstrItinData<IIC_fpSQRT64 , [InstrStage<29, [V6_Pipe]>], [34, 2, 2]>, // - // Integer to Single-precision Move - InstrItinData<IIC_fpMOVIS, [InstrStage<1, [V6_Pipe]>], [10, 1]>, - // - // Integer to Double-precision Move - InstrItinData<IIC_fpMOVID, [InstrStage<1, [V6_Pipe]>], [10, 1, 1]>, - // - // Single-precision to Integer Move - InstrItinData<IIC_fpMOVSI, [InstrStage<1, [V6_Pipe]>], [10, 1]>, - // - // Double-precision to Integer Move - InstrItinData<IIC_fpMOVDI, [InstrStage<1, [V6_Pipe]>], [10, 10, 1]>, - // // Single-precision FP Load InstrItinData<IIC_fpLoad32 , [InstrStage<1, [V6_Pipe]>], [5, 2, 2]>, // |