diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2008-03-12 07:02:50 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2008-03-12 07:02:50 +0000 |
| commit | c8e3b147eea6155eb047340205730b5332259bb6 (patch) | |
| tree | 653f2c86265e5157f851d3854a28ccb7d5ada8f8 /lib | |
| parent | dfd07eab24394659ad445d6f7998fa31c1908d73 (diff) | |
Clean up my own mess.
X86 lowering normalize vector 0 to v4i32. However DAGCombine can fold (sub x, x) -> 0 after legalization. It can create a zero vector of a type that's not expected (e.g. v8i16). We don't want to disable the optimization since leaving a (sub x, x) is really bad. Add isel patterns for other types of vector 0 to ensure correctness. It's highly unlikely to happen other than in bugpoint reduced test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48279 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrMMX.td | 6 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 8 |
3 files changed, 15 insertions, 7 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 5a6077a3ca..0e719f844e 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1102,14 +1102,8 @@ SDOperand DAGCombiner::visitSUB(SDNode *N) { } // fold (sub x, x) -> 0 - if (N0 == N1) { - if (AfterLegalize && ISD::isBuildVectorAllZeros(N0.Val)) - // For example, zero vectors might be normalized to a particular vector - // type to ensure they are CSE'd. Avoid issuing zero vector nodes of - // *unexpected* type after legalization. - return N0; + if (N0 == N1) return DAG.getConstant(0, N->getValueType(0)); - } // fold (sub c1, c2) -> c1-c2 if (N0C && N1C) return DAG.getNode(ISD::SUB, VT, N0, N1); diff --git a/lib/Target/X86/X86InstrMMX.td b/lib/Target/X86/X86InstrMMX.td index 65013b3914..0a18fa53f1 100644 --- a/lib/Target/X86/X86InstrMMX.td +++ b/lib/Target/X86/X86InstrMMX.td @@ -510,6 +510,12 @@ let isReMaterializable = 1 in { [(set VR64:$dst, (v2i32 immAllOnesV))]>; } +let Predicates = [HasMMX] in { + def : Pat<(v1i64 immAllZerosV), (MMX_V_SET0)>; + def : Pat<(v4i16 immAllZerosV), (MMX_V_SET0)>; + def : Pat<(v8i8 immAllZerosV), (MMX_V_SET0)>; +} + //===----------------------------------------------------------------------===// // Non-Instruction Patterns //===----------------------------------------------------------------------===// diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 55d92bdfa6..0ca9c69c00 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -969,6 +969,14 @@ def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "xorps\t$dst, $dst", [(set VR128:$dst, (v4i32 immAllZerosV))]>; +let Predicates = [HasSSE1] in { + def : Pat<(v2i64 immAllZerosV), (V_SET0)>; + def : Pat<(v8i16 immAllZerosV), (V_SET0)>; + def : Pat<(v16i8 immAllZerosV), (V_SET0)>; + def : Pat<(v2f64 immAllZerosV), (V_SET0)>; + def : Pat<(v4f32 immAllZerosV), (V_SET0)>; +} + // FR32 to 128-bit vector conversion. def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src), "movss\t{$src, $dst|$dst, $src}", |