diff options
| author | Bob Wilson <bob.wilson@apple.com> | 2010-11-27 06:35:09 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-11-27 06:35:09 +0000 |
| commit | 8d412946643f048daa9d76b4f021a172341ea045 (patch) | |
| tree | 1b72742427d13785dcec32631af9f4187006982e /lib | |
| parent | ad1252498d37fdf32c92569fe35bf09bb6e78caa (diff) | |
Fix incorrect scheduling itineraries for NEON vld1/vst1 instructions.
I added these instructions recently but I have no idea where these "1"
values in the NextCycles field came from. As far as I can tell now,
these instruction stages are clearly intended to overlap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120193 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA8.td | 8 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA9.td | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/lib/Target/ARM/ARMScheduleA8.td b/lib/Target/ARM/ARMScheduleA8.td index bd5e2749ea..bcd6c78ae9 100644 --- a/lib/Target/ARM/ARMScheduleA8.td +++ b/lib/Target/ARM/ARMScheduleA8.td @@ -465,13 +465,13 @@ def CortexA8Itineraries : ProcessorItineraries< // // VLD1ln InstrItinData<IIC_VLD1ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<3, [A8_NLSPipe], 1>, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [3, 1, 1, 1]>, // // VLD1lnu InstrItinData<IIC_VLD1lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<3, [A8_NLSPipe], 1>, + InstrStage<3, [A8_NLSPipe], 0>, InstrStage<3, [A8_LSPipe]>], [3, 2, 1, 1, 1, 1]>, // @@ -609,13 +609,13 @@ def CortexA8Itineraries : ProcessorItineraries< // // VST1ln InstrItinData<IIC_VST1ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<2, [A8_NLSPipe], 1>, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [1, 1, 1]>, // // VST1lnu InstrItinData<IIC_VST1lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, - InstrStage<2, [A8_NLSPipe], 1>, + InstrStage<2, [A8_NLSPipe], 0>, InstrStage<2, [A8_LSPipe]>], [2, 1, 1, 1, 1]>, // diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td index 4a398c4656..14bfdb7578 100644 --- a/lib/Target/ARM/ARMScheduleA9.td +++ b/lib/Target/ARM/ARMScheduleA9.td @@ -800,7 +800,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [4, 1, 1, 1]>, // @@ -809,7 +809,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<9, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [4, 2, 1, 1, 1, 1]>, // @@ -1018,7 +1018,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<2, [A9_DRegsVFP], 0, Reserved>, - InstrStage<2, [A9_NPipe], 1>, + InstrStage<2, [A9_NPipe], 0>, InstrStage<2, [A9_LSUnit]>], [1, 1, 1]>, // @@ -1027,7 +1027,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_MUX0], 0>, InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, - InstrStage<3, [A9_NPipe], 1>, + InstrStage<3, [A9_NPipe], 0>, InstrStage<3, [A9_LSUnit]>], [2, 1, 1, 1, 1]>, // |