diff options
| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-09-27 01:56:38 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-09-27 01:56:38 +0000 |
| commit | 7e105bcc3ab0e0e8ddc7617b37a9fe9cd1d0b1bf (patch) | |
| tree | 6744ed56ec9e40007417781994fd034f3fcf783c /lib | |
| parent | 7509ec18d100206cd44790641e012aae35714212 (diff) | |
MIPS DSP: add bitcast patterns between vectors and int.
No test cases. These patterns will get tested along with dsp intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164746 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/Mips/MipsDSPInstrInfo.td | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsDSPInstrInfo.td b/lib/Target/Mips/MipsDSPInstrInfo.td index 556cf6bc50..b9f40efbd1 100644 --- a/lib/Target/Mips/MipsDSPInstrInfo.td +++ b/lib/Target/Mips/MipsDSPInstrInfo.td @@ -23,6 +23,16 @@ def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>; class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> : Pat<pattern, result>, Requires<[pred]>; +class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC, + RegisterClass SrcRC> : + DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))), + (COPY_TO_REGCLASS SrcRC:$src, DstRC)>; + +def : BitconvertPat<i32, v2i16, CPURegs, DSPRegs>; +def : BitconvertPat<i32, v4i8, CPURegs, DSPRegs>; +def : BitconvertPat<v2i16, i32, DSPRegs, CPURegs>; +def : BitconvertPat<v4i8, i32, DSPRegs, CPURegs>; + def : DSPPat<(v2i16 (load addr:$a)), (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>; def : DSPPat<(v4i8 (load addr:$a)), |