Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize

it accordingly. Thanks to Jakob Stoklund Olesen for pointing
out how this might be useful.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68986 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 29 insertions, 30 deletions

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
index cd969dc733..2a278b749a 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
@@ -134,10 +134,10 @@ namespace llvm {
     void EmitSubregNode(SDNode *Node, 
                         DenseMap<SDValue, unsigned> &VRBaseMap);
 
-    /// EmitCopyToSubclassNode - Generate machine code for COPY_TO_SUBCLASS
+    /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS
     /// nodes.
     ///
-    void EmitCopyToSubclassNode(SDNode *Node,
+    void EmitCopyToRegClassNode(SDNode *Node,
                                 DenseMap<SDValue, unsigned> &VRBaseMap);
 
     /// getVR - Return the virtual register corresponding to the specified result
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
index 084ecb7555..94333d3445 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
@@ -464,12 +464,12 @@ void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
   assert(isNew && "Node emitted out of order - early");
 }
 
-/// EmitCopyToSubclassNode - Generate machine code for COPY_TO_SUBCLASS nodes.
-/// COPY_TO_SUBCLASS is just a normal copy, except that the destination
+/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
+/// COPY_TO_REGCLASS is just a normal copy, except that the destination
 /// register is constrained to be in a particular register class.
 ///
 void
-ScheduleDAGSDNodes::EmitCopyToSubclassNode(SDNode *Node,
+ScheduleDAGSDNodes::EmitCopyToRegClassNode(SDNode *Node,
                                        DenseMap<SDValue, unsigned> &VRBaseMap) {
   unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
   const TargetRegisterClass *SrcRC = MRI.getRegClass(VReg);
@@ -477,19 +477,18 @@ ScheduleDAGSDNodes::EmitCopyToSubclassNode(SDNode *Node,
   unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
   const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx);
 
-  assert(SrcRC->hasSubClass(DstRC) &&
-         "COPY_TO_SUBCLASS destination class is not a proper subclass!");
-
   // Create the new VReg in the destination class and emit a copy.
   unsigned NewVReg = MRI.createVirtualRegister(DstRC);
   bool Emitted = TII->copyRegToReg(*BB, InsertPos, NewVReg, VReg,
                                    DstRC, SrcRC);
-  // If the target didn't handle that, emit a plain copy.
-  if (!Emitted)
+  // If the target didn't handle the copy with different register
+  // classes and the destination is a subset of the source,
+  // try a normal same-RC copy.
+  if (!Emitted && SrcRC->hasSubClass(DstRC))
     Emitted = TII->copyRegToReg(*BB, InsertPos, NewVReg, VReg,
                                 SrcRC, SrcRC);
   assert(Emitted &&
-         "Unable to issue a copy instruction for a COPY_TO_SUBCLASS node!\n");
+         "Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n");
 
   SDValue Op(Node, 0);
   bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
@@ -513,9 +512,9 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
       return;
     }
 
-    // Handle COPY_TO_SUBCLASS specially.
-    if (Opc == TargetInstrInfo::COPY_TO_SUBCLASS) {
-      EmitCopyToSubclassNode(Node, VRBaseMap);
+    // Handle COPY_TO_REGCLASS specially.
+    if (Opc == TargetInstrInfo::COPY_TO_REGCLASS) {
+      EmitCopyToRegClassNode(Node, VRBaseMap);
       return;
     }
 
diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td
index 05bccabc30..1785bd1331 100644
--- a/lib/Target/X86/X86Instr64bit.td
+++ b/lib/Target/X86/X86Instr64bit.td
@@ -1578,18 +1578,18 @@ def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
           (SUBREG_TO_REG
             (i64 0),
             (MOVZX32_NOREXrr8
-              (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR64:$src, GR64_),
+              (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_),
                               x86_subreg_8bit_hi)),
             x86_subreg_32bit)>;
 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
           (MOVZX32_NOREXrr8
-            (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR32:$src, GR32_),
+            (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
                             x86_subreg_8bit_hi))>,
       Requires<[In64BitMode]>;
 def : Pat<(srl_su GR16:$src, (i8 8)),
           (EXTRACT_SUBREG
             (MOVZX32_NOREXrr8
-              (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR16:$src, GR16_),
+              (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
                               x86_subreg_8bit_hi)),
             x86_subreg_16bit)>,
       Requires<[In64BitMode]>;
@@ -1598,18 +1598,18 @@ def : Pat<(srl_su GR16:$src, (i8 8)),
 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
           (MOV8mr_NOREX
             addr:$dst,
-            (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR64:$src, GR64_),
+            (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_),
                             x86_subreg_8bit_hi))>;
 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
           (MOV8mr_NOREX
             addr:$dst,
-            (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR32:$src, GR32_),
+            (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
                             x86_subreg_8bit_hi))>,
       Requires<[In64BitMode]>;
 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
           (MOV8mr_NOREX
             addr:$dst,
-            (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR16:$src, GR16_),
+            (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
                             x86_subreg_8bit_hi))>,
       Requires<[In64BitMode]>;
 
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 830796e3a3..077b4563b0 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -3349,12 +3349,12 @@ def : Pat<(and GR32:$src1, 0xffff),
           (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
 // r & (2^8-1) ==> movz
 def : Pat<(and GR32:$src1, 0xff),
-          (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR32:$src1, GR32_),
+          (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src1, GR32_),
                                       x86_subreg_8bit))>,
       Requires<[In32BitMode]>;
 // r & (2^8-1) ==> movz
 def : Pat<(and GR16:$src1, 0xff),
-          (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR16:$src1, GR16_),
+          (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src1, GR16_),
                                       x86_subreg_8bit))>,
       Requires<[In32BitMode]>;
 
@@ -3362,11 +3362,11 @@ def : Pat<(and GR16:$src1, 0xff),
 def : Pat<(sext_inreg GR32:$src, i16),
           (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
 def : Pat<(sext_inreg GR32:$src, i8),
-          (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR32:$src, GR32_),
+          (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
                                       x86_subreg_8bit))>,
       Requires<[In32BitMode]>;
 def : Pat<(sext_inreg GR16:$src, i8),
-          (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR16:$src, GR16_),
+          (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
                                       x86_subreg_8bit))>,
       Requires<[In32BitMode]>;
 
@@ -3374,32 +3374,32 @@ def : Pat<(sext_inreg GR16:$src, i8),
 def : Pat<(i16 (trunc GR32:$src)),
           (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
 def : Pat<(i8 (trunc GR32:$src)),
-          (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR32:$src, GR32_),
+          (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
                           x86_subreg_8bit)>,
       Requires<[In32BitMode]>;
 def : Pat<(i8 (trunc GR16:$src)),
-          (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR16:$src, GR16_),
+          (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
                           x86_subreg_8bit)>,
       Requires<[In32BitMode]>;
 
 // h-register tricks
 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
-          (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR16:$src, GR16_),
+          (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
                           x86_subreg_8bit_hi)>,
       Requires<[In32BitMode]>;
 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
-          (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR32:$src, GR32_),
+          (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
                           x86_subreg_8bit_hi)>,
       Requires<[In32BitMode]>;
 def : Pat<(srl_su GR16:$src, (i8 8)),
           (EXTRACT_SUBREG
             (MOVZX32rr8
-              (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR16:$src, GR16_),
+              (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
                               x86_subreg_8bit_hi)),
             x86_subreg_16bit)>,
       Requires<[In32BitMode]>;
 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
-          (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR32:$src, GR32_),
+          (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
                                       x86_subreg_8bit_hi))>,
       Requires<[In32BitMode]>;