diff options
author | Duraid Madina <duraid@octopus.com.au> | 2005-05-02 07:27:14 +0000 |
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committer | Duraid Madina <duraid@octopus.com.au> | 2005-05-02 07:27:14 +0000 |
commit | 40c9e6be3e836f1e27c56f51ed796c081870832d (patch) | |
tree | a9b09d22ea098c07a54a449e975eb6461842ad10 /lib | |
parent | 4bd708d8a6d846e5e917b7f660055b578ba0e093 (diff) |
support multiplication by constant negative integers
this constmul code is still buggy though, so beware. mul by 7427 is currently
broken, for example. will fix it when I get a moment :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21652 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/IA64/IA64ISelPattern.cpp | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp index 5ac5df5c93..badc89f814 100644 --- a/lib/Target/IA64/IA64ISelPattern.cpp +++ b/lib/Target/IA64/IA64ISelPattern.cpp @@ -784,7 +784,7 @@ SDOperand ISel::BuildConstmulSequence(SDOperand N) { bool flippedSign; unsigned preliminaryShift=0; - assert(constant > 0 && "erk, don't multiply by zero or negative nums\n"); + assert(constant != 0 && "erk, you're trying to multiply by constant zero\n"); // first, we make the constant to multiply by positive if(constant<0) { @@ -832,15 +832,24 @@ SDOperand ISel::BuildConstmulSequence(SDOperand N) { } // don't forget flippedSign and preliminaryShift! - SDOperand finalresult; + SDOperand shiftedresult; if(preliminaryShift) { SDOperand finalshift = ISelDAG->getConstant(preliminaryShift, MVT::i64); - finalresult = ISelDAG->getNode(ISD::SHL, MVT::i64, + shiftedresult = ISelDAG->getNode(ISD::SHL, MVT::i64, results[ops.size()-1], finalshift); } else { // there was no preliminary divide-by-power-of-2 required - finalresult = results[ops.size()-1]; + shiftedresult = results[ops.size()-1]; } + SDOperand finalresult; + if(flippedSign) { // if we were multiplying by a negative constant: + SDOperand zero = ISelDAG->getConstant(0, MVT::i64); + // subtract the result from 0 to flip its sign + finalresult = ISelDAG->getNode(ISD::SUB, MVT::i64, zero, shiftedresult); + } else { // there was no preliminary multiply by -1 required + finalresult = shiftedresult; + } + return finalresult; } |