Enabling new condition code modeling scheme.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42459 91177308-0d34-0410-b5e6-96231b3b80d8

10 files changed, 308 insertions, 1649 deletions

diff --git a/lib/Target/TargetMachine.cpp b/lib/Target/TargetMachine.cpp
index 3c00428a46..6c00a3f492 100644
--- a/lib/Target/TargetMachine.cpp
+++ b/lib/Target/TargetMachine.cpp
@@ -31,7 +31,6 @@ namespace llvm {
   bool UseSoftFloat;
   bool NoZerosInBSS;
   bool ExceptionHandling;
-  bool NewCCModeling;
   Reloc::Model RelocationModel;
   CodeModel::Model CMModel;
 }
@@ -117,11 +116,6 @@ namespace {
       clEnumValN(CodeModel::Large, "large",
                  "  Large code model"),
       clEnumValEnd));
-  cl::opt<bool, true>
-  EnableNewCCModeling("new-cc-modeling-scheme",
-                      cl::desc("New CC modeling scheme."),
-                      cl::location(NewCCModeling),
-                      cl::init(false));
 }
 
 //---------------------------------------------------------------------------
diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp
index 37a9f6016c..90813b57ef 100644
--- a/lib/Target/X86/X86FloatingPoint.cpp
+++ b/lib/Target/X86/X86FloatingPoint.cpp
@@ -437,39 +437,6 @@ static const TableEntry OpcodeTable[] = {
   { X86::MUL_FpI32m32 , X86::MUL_FI32m },
   { X86::MUL_FpI32m64 , X86::MUL_FI32m },
   { X86::MUL_FpI32m80 , X86::MUL_FI32m },
-
-  // TEMPORARY
-  { X86::NEW_CMOVBE_Fp32  , X86::CMOVBE_F  },
-  { X86::NEW_CMOVBE_Fp64  , X86::CMOVBE_F  },
-  { X86::NEW_CMOVBE_Fp80  , X86::CMOVBE_F  },
-  { X86::NEW_CMOVB_Fp32   , X86::CMOVB_F   },
-  { X86::NEW_CMOVB_Fp64   , X86::CMOVB_F  },
-  { X86::NEW_CMOVB_Fp80   , X86::CMOVB_F  },
-  { X86::NEW_CMOVE_Fp32   , X86::CMOVE_F  },
-  { X86::NEW_CMOVE_Fp64   , X86::CMOVE_F   },
-  { X86::NEW_CMOVE_Fp80   , X86::CMOVE_F   },
-  { X86::NEW_CMOVNBE_Fp32 , X86::CMOVNBE_F },
-  { X86::NEW_CMOVNBE_Fp64 , X86::CMOVNBE_F },
-  { X86::NEW_CMOVNBE_Fp80 , X86::CMOVNBE_F },
-  { X86::NEW_CMOVNB_Fp32  , X86::CMOVNB_F  },
-  { X86::NEW_CMOVNB_Fp64  , X86::CMOVNB_F  },
-  { X86::NEW_CMOVNB_Fp80  , X86::CMOVNB_F  },
-  { X86::NEW_CMOVNE_Fp32  , X86::CMOVNE_F  },
-  { X86::NEW_CMOVNE_Fp64  , X86::CMOVNE_F  },
-  { X86::NEW_CMOVNE_Fp80  , X86::CMOVNE_F  },
-  { X86::NEW_CMOVNP_Fp32  , X86::CMOVNP_F  },
-  { X86::NEW_CMOVNP_Fp64  , X86::CMOVNP_F  },
-  { X86::NEW_CMOVNP_Fp80  , X86::CMOVNP_F  },
-  { X86::NEW_CMOVP_Fp32   , X86::CMOVP_F   },
-  { X86::NEW_CMOVP_Fp64   , X86::CMOVP_F   },
-  { X86::NEW_CMOVP_Fp80   , X86::CMOVP_F   },
-  { X86::NEW_UCOM_FpIr32  , X86::UCOM_FIr  },
-  { X86::NEW_UCOM_FpIr64  , X86::UCOM_FIr  },
-  { X86::NEW_UCOM_FpIr80  , X86::UCOM_FIr  },
-  { X86::NEW_UCOM_Fpr32   , X86::UCOM_Fr   },
-  { X86::NEW_UCOM_Fpr64   , X86::UCOM_Fr   },
-  { X86::NEW_UCOM_Fpr80   , X86::UCOM_Fr   },
-
   { X86::SIN_Fp32     , X86::SIN_F     },
   { X86::SIN_Fp64     , X86::SIN_F     },
   { X86::SIN_Fp80     , X86::SIN_F     },
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 6d3e4db38d..9dc4dd69c2 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -3356,15 +3356,12 @@ SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
     const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
     SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
                                     DAG.getConstant(32, MVT::i8));
-    SDOperand COps[]={DAG.getEntryNode(), AndNode, DAG.getConstant(0, MVT::i8)};
-    SDOperand Cond = NewCCModeling
-      ? DAG.getNode(X86ISD::CMP_NEW, MVT::i32,
-                    AndNode, DAG.getConstant(0, MVT::i8))
-      : DAG.getNode(X86ISD::CMP, VTs, 2, COps, 3).getValue(1);
+    SDOperand Cond = DAG.getNode(X86ISD::CMP, MVT::i32,
+                                 AndNode, DAG.getConstant(0, MVT::i8));
 
     SDOperand Hi, Lo;
     SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
-    unsigned Opc = NewCCModeling ? X86ISD::CMOV_NEW : X86ISD::CMOV;
+    unsigned Opc = X86ISD::CMOV;
     VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
     SmallVector<SDOperand, 4> Ops;
     if (Op.getOpcode() == ISD::SHL_PARTS) {
@@ -3372,43 +3369,27 @@ SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
       Ops.push_back(Tmp3);
       Ops.push_back(CC);
       Ops.push_back(Cond);
-      if (NewCCModeling)
-        Hi = DAG.getNode(Opc, MVT::i32, &Ops[0], Ops.size());
-      else {
-        Hi = DAG.getNode(Opc, VTs, 2, &Ops[0], Ops.size());
-        Cond = Hi.getValue(1);
-      }
+      Hi = DAG.getNode(Opc, MVT::i32, &Ops[0], Ops.size());
 
       Ops.clear();
       Ops.push_back(Tmp3);
       Ops.push_back(Tmp1);
       Ops.push_back(CC);
       Ops.push_back(Cond);
-      if (NewCCModeling) 
-        Lo = DAG.getNode(Opc, MVT::i32, &Ops[0], Ops.size());
-      else
-        Lo = DAG.getNode(Opc, VTs, 2, &Ops[0], Ops.size());
+      Lo = DAG.getNode(Opc, MVT::i32, &Ops[0], Ops.size());
     } else {
       Ops.push_back(Tmp2);
       Ops.push_back(Tmp3);
       Ops.push_back(CC);
       Ops.push_back(Cond);
-      if (NewCCModeling)
-        Lo = DAG.getNode(Opc, MVT::i32, &Ops[0], Ops.size());
-      else {
-        Lo = DAG.getNode(Opc, VTs, 2, &Ops[0], Ops.size());
-        Cond = Lo.getValue(1);
-      }
+      Lo = DAG.getNode(Opc, MVT::i32, &Ops[0], Ops.size());
 
       Ops.clear();
       Ops.push_back(Tmp3);
       Ops.push_back(Tmp1);
       Ops.push_back(CC);
       Ops.push_back(Cond);
-      if (NewCCModeling)
-        Hi = DAG.getNode(Opc, MVT::i32, &Ops[0], Ops.size());
-      else
-        Hi = DAG.getNode(Opc, VTs, 2, &Ops[0], Ops.size());
+      Hi = DAG.getNode(Opc, MVT::i32, &Ops[0], Ops.size());
     }
 
     VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32);
@@ -3674,54 +3655,7 @@ SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
   return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
 }
 
-SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG,
-                                        SDOperand Chain) {
-  assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
-  SDOperand Cond;
-  SDOperand Op0 = Op.getOperand(0);
-  SDOperand Op1 = Op.getOperand(1);
-  SDOperand CC = Op.getOperand(2);
-  ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
-  const MVT::ValueType *VTs1 = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
-  const MVT::ValueType *VTs2 = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
-  bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
-  unsigned X86CC;
-
-  if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
-                     Op0, Op1, DAG)) {
-    SDOperand Ops1[] = { Chain, Op0, Op1 };
-    Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, Ops1, 3).getValue(1);
-    SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
-    return DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
-  }
-
-  assert(isFP && "Illegal integer SetCC!");
-
-  SDOperand COps[] = { Chain, Op0, Op1 };
-  Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, COps, 3).getValue(1);
-
-  switch (SetCCOpcode) {
-  default: assert(false && "Illegal floating point SetCC!");
-  case ISD::SETOEQ: {  // !PF & ZF
-    SDOperand Ops1[] = { DAG.getConstant(X86::COND_NP, MVT::i8), Cond };
-    SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
-    SDOperand Ops2[] = { DAG.getConstant(X86::COND_E, MVT::i8),
-                         Tmp1.getValue(1) };
-    SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
-    return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
-  }
-  case ISD::SETUNE: {  // PF | !ZF
-    SDOperand Ops1[] = { DAG.getConstant(X86::COND_P, MVT::i8), Cond };
-    SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
-    SDOperand Ops2[] = { DAG.getConstant(X86::COND_NE, MVT::i8),
-                         Tmp1.getValue(1) };
-    SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
-    return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
-  }
-  }
-}
-
-SDOperand X86TargetLowering::LowerSETCC_New(SDOperand Op, SelectionDAG &DAG) {
+SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
   assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
   SDOperand Cond;
   SDOperand Op0 = Op.getOperand(0);
@@ -3733,27 +3667,27 @@ SDOperand X86TargetLowering::LowerSETCC_New(SDOperand Op, SelectionDAG &DAG) {
 
   if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
                      Op0, Op1, DAG)) {
-    Cond = DAG.getNode(X86ISD::CMP_NEW, MVT::i32, Op0, Op1);
-    return DAG.getNode(X86ISD::SETCC_NEW, MVT::i8,
+    Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
+    return DAG.getNode(X86ISD::SETCC, MVT::i8,
                        DAG.getConstant(X86CC, MVT::i8), Cond);
   }
 
   assert(isFP && "Illegal integer SetCC!");
 
-  Cond = DAG.getNode(X86ISD::CMP_NEW, MVT::i32, Op0, Op1);
+  Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
   switch (SetCCOpcode) {
   default: assert(false && "Illegal floating point SetCC!");
   case ISD::SETOEQ: {  // !PF & ZF
-    SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC_NEW, MVT::i8,
+    SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
                                  DAG.getConstant(X86::COND_NP, MVT::i8), Cond);
-    SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC_NEW, MVT::i8,
+    SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
                                  DAG.getConstant(X86::COND_E, MVT::i8), Cond);
     return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
   }
   case ISD::SETUNE: {  // PF | !ZF
-    SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC_NEW, MVT::i8,
+    SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
                                  DAG.getConstant(X86::COND_P, MVT::i8), Cond);
-    SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC_NEW, MVT::i8,
+    SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
                                  DAG.getConstant(X86::COND_NE, MVT::i8), Cond);
     return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
   }
@@ -3763,13 +3697,11 @@ SDOperand X86TargetLowering::LowerSETCC_New(SDOperand Op, SelectionDAG &DAG) {
 
 SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
   bool addTest = true;
-  SDOperand Chain = DAG.getEntryNode();
   SDOperand Cond  = Op.getOperand(0);
   SDOperand CC;
-  const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
 
   if (Cond.getOpcode() == ISD::SETCC)
-    Cond = LowerSETCC(Cond, DAG, Chain);
+    Cond = LowerSETCC(Cond, DAG);
 
   if (Cond.getOpcode() == X86ISD::SETCC) {
     CC = Cond.getOperand(0);
@@ -3786,58 +3718,9 @@ SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
       ! ((X86ScalarSSEf32 && Op.getValueType()==MVT::f32) ||
          (X86ScalarSSEf64 && Op.getValueType()==MVT::f64)) &&
       !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
-    if ((Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) &&
-        !IllegalFPCMov) {
-      SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
-      Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
-      addTest = false;
-    }
-  }
-
-  if (addTest) {
-    CC = DAG.getConstant(X86::COND_NE, MVT::i8);
-    SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
-    Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
-  }
-
-  VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::Flag);
-  SmallVector<SDOperand, 4> Ops;
-  // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
-  // condition is true.
-  Ops.push_back(Op.getOperand(2));
-  Ops.push_back(Op.getOperand(1));
-  Ops.push_back(CC);
-  Ops.push_back(Cond.getValue(1));
-  return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
-}
-
-SDOperand X86TargetLowering::LowerSELECT_New(SDOperand Op, SelectionDAG &DAG) {
-  bool addTest = true;
-  SDOperand Cond  = Op.getOperand(0);
-  SDOperand CC;
-
-  if (Cond.getOpcode() == ISD::SETCC)
-    Cond = LowerSETCC_New(Cond, DAG);
-
-  if (Cond.getOpcode() == X86ISD::SETCC_NEW) {
-    CC = Cond.getOperand(0);
-
-    // If condition flag is set by a X86ISD::CMP, then make a copy of it
-    // (since flag operand cannot be shared). Use it as the condition setting
-    // operand in place of the X86ISD::SETCC.
-    // If the X86ISD::SETCC has more than one use, then perhaps it's better
-    // to use a test instead of duplicating the X86ISD::CMP (for register
-    // pressure reason)?
-    SDOperand Cmp = Cond.getOperand(1);
-    unsigned Opc = Cmp.getOpcode();
-    bool IllegalFPCMov = 
-      ! ((X86ScalarSSEf32 && Op.getValueType()==MVT::f32) ||
-         (X86ScalarSSEf64 && Op.getValueType()==MVT::f64)) &&
-      !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
-    if ((Opc == X86ISD::CMP_NEW ||
-         Opc == X86ISD::COMI_NEW ||
-         Opc == X86ISD::UCOMI_NEW) &&
-        !IllegalFPCMov) {
+    if ((Opc == X86ISD::CMP ||
+         Opc == X86ISD::COMI ||
+         Opc == X86ISD::UCOMI) && !IllegalFPCMov) {
       Cond = DAG.getNode(Opc, MVT::i32, Cmp.getOperand(0), Cmp.getOperand(1));
       addTest = false;
     }
@@ -3845,7 +3728,7 @@ SDOperand X86TargetLowering::LowerSELECT_New(SDOperand Op, SelectionDAG &DAG) {
 
   if (addTest) {
     CC = DAG.getConstant(X86::COND_NE, MVT::i8);
-    Cond = DAG.getNode(X86ISD::CMP_NEW, MVT::i32, Cond,
+    Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Cond,
                        DAG.getConstant(0, MVT::i8));
   }
 
@@ -3858,7 +3741,7 @@ SDOperand X86TargetLowering::LowerSELECT_New(SDOperand Op, SelectionDAG &DAG) {
   Ops.push_back(Op.getOperand(1));
   Ops.push_back(CC);
   Ops.push_back(Cond);
-  return DAG.getNode(X86ISD::CMOV_NEW, VTs, 2, &Ops[0], Ops.size());
+  return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
 }
 
 SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
@@ -3867,10 +3750,9 @@ SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
   SDOperand Cond  = Op.getOperand(1);
   SDOperand Dest  = Op.getOperand(2);
   SDOperand CC;
-  const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
 
   if (Cond.getOpcode() == ISD::SETCC)
-    Cond = LowerSETCC(Cond, DAG, Chain);
+    Cond = LowerSETCC(Cond, DAG);
 
   if (Cond.getOpcode() == X86ISD::SETCC) {
     CC = Cond.getOperand(0);
@@ -3883,46 +3765,9 @@ SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
     // pressure reason)?
     SDOperand Cmp = Cond.getOperand(1);
     unsigned Opc = Cmp.getOpcode();
-    if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) {
-      SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
-      Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
-      addTest = false;
-    }
-  }
-
-  if (addTest) {
-    CC = DAG.getConstant(X86::COND_NE, MVT::i8);
-    SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
-    Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
-  }
-  return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
-                     Cond, Op.getOperand(2), CC, Cond.getValue(1));
-}
-
-SDOperand X86TargetLowering::LowerBRCOND_New(SDOperand Op, SelectionDAG &DAG) {
-  bool addTest = true;
-  SDOperand Chain = Op.getOperand(0);
-  SDOperand Cond  = Op.getOperand(1);
-  SDOperand Dest  = Op.getOperand(2);
-  SDOperand CC;
-
-  if (Cond.getOpcode() == ISD::SETCC)
-    Cond = LowerSETCC_New(Cond, DAG);
-
-  if (Cond.getOpcode() == X86ISD::SETCC_NEW) {
-    CC = Cond.getOperand(0);
-
-    // If condition flag is set by a X86ISD::CMP, then make a copy of it
-    // (since flag operand cannot be shared). Use it as the condition setting
-    // operand in place of the X86ISD::SETCC.
-    // If the X86ISD::SETCC has more than one use, then perhaps it's better
-    // to use a test instead of duplicating the X86ISD::CMP (for register
-    // pressure reason)?
-    SDOperand Cmp = Cond.getOperand(1);
-    unsigned Opc = Cmp.getOpcode();
-    if (Opc == X86ISD::CMP_NEW ||
-        Opc == X86ISD::COMI_NEW ||
-        Opc == X86ISD::UCOMI_NEW) {
+    if (Opc == X86ISD::CMP ||
+        Opc == X86ISD::COMI ||
+        Opc == X86ISD::UCOMI) {
       Cond = DAG.getNode(Opc, MVT::i32, Cmp.getOperand(0), Cmp.getOperand(1));
       addTest = false;
     }
@@ -3930,9 +3775,9 @@ SDOperand X86TargetLowering::LowerBRCOND_New(SDOperand Op, SelectionDAG &DAG) {
 
   if (addTest) {
     CC = DAG.getConstant(X86::COND_NE, MVT::i8);
-    Cond= DAG.getNode(X86ISD::CMP_NEW, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
+    Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
   }
-  return DAG.getNode(X86ISD::BRCOND_NEW, Op.getValueType(),
+  return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
                      Chain, Op.getOperand(2), CC, Cond);
 }
 
@@ -4535,21 +4380,10 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
     SDOperand RHS = Op.getOperand(2);
     translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
 
-    if (NewCCModeling) {
-      Opc = (Opc == X86ISD::UCOMI) ? X86ISD::UCOMI_NEW : X86ISD::COMI_NEW;
-      SDOperand Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
-      SDOperand SetCC = DAG.getNode(X86ISD::SETCC_NEW, MVT::i8,
-                                    DAG.getConstant(X86CC, MVT::i8), Cond);
-      return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
-    } else {
-      const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
-      SDOperand Ops1[] = { DAG.getEntryNode(), LHS, RHS };
-      SDOperand Cond = DAG.getNode(Opc, VTs, 2, Ops1, 3);
-      VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
-      SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
-      SDOperand SetCC = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2);
-      return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
-    }
+    SDOperand Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
+    SDOperand SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
+                                  DAG.getConstant(X86CC, MVT::i8), Cond);
+    return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
   }
   }
 }
@@ -4721,15 +4555,9 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
   case ISD::FABS:               return LowerFABS(Op, DAG);
   case ISD::FNEG:               return LowerFNEG(Op, DAG);
   case ISD::FCOPYSIGN:          return LowerFCOPYSIGN(Op, DAG);
-  case ISD::SETCC:              return NewCCModeling
-                                  ? LowerSETCC_New(Op, DAG)
-                                  : LowerSETCC(Op, DAG, DAG.getEntryNode());
-  case ISD::SELECT:             return NewCCModeling
-                                  ? LowerSELECT_New(Op, DAG)
-                                  : LowerSELECT(Op, DAG);
-  case ISD::BRCOND:             return NewCCModeling
-                                  ? LowerBRCOND_New(Op, DAG)
-                                  : LowerBRCOND(Op, DAG);
+  case ISD::SETCC:              return LowerSETCC(Op, DAG);
+  case ISD::SELECT:             return LowerSELECT(Op, DAG);
+  case ISD::BRCOND:             return LowerBRCOND(Op, DAG);
   case ISD::JumpTable:          return LowerJumpTable(Op, DAG);
   case ISD::CALL:               return LowerCALL(Op, DAG);
   case ISD::RET:                return LowerRET(Op, DAG);
@@ -4773,17 +4601,11 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
   case X86ISD::TAILCALL:           return "X86ISD::TAILCALL";
   case X86ISD::RDTSC_DAG:          return "X86ISD::RDTSC_DAG";
   case X86ISD::CMP:                return "X86ISD::CMP";
-  case X86ISD::CMP_NEW:            return "X86ISD::CMP_NEW";
   case X86ISD::COMI:               return "X86ISD::COMI";
-  case X86ISD::COMI_NEW:           return "X86ISD::COMI_NEW";
   case X86ISD::UCOMI:              return "X86ISD::UCOMI";
-  case X86ISD::UCOMI_NEW:          return "X86ISD::UCOMI_NEW";
   case X86ISD::SETCC:              return "X86ISD::SETCC";
-  case X86ISD::SETCC_NEW:          return "X86ISD::SETCC_NEW";
   case X86ISD::CMOV:               return "X86ISD::CMOV";
-  case X86ISD::CMOV_NEW:           return "X86ISD::CMOV_NEW";
   case X86ISD::BRCOND:             return "X86ISD::BRCOND";
-  case X86ISD::BRCOND_NEW:         return "X86ISD::BRCOND_NEW";
   case X86ISD::RET_FLAG:           return "X86ISD::RET_FLAG";
   case X86ISD::REP_STOS:           return "X86ISD::REP_STOS";
   case X86ISD::REP_MOVS:           return "X86ISD::REP_MOVS";
@@ -4902,13 +4724,7 @@ X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
   case X86::CMOV_FR64:
   case X86::CMOV_V4F32:
   case X86::CMOV_V2F64:
-  case X86::CMOV_V2I64:
-
-  case X86::NEW_CMOV_FR32:
-  case X86::NEW_CMOV_FR64:
-  case X86::NEW_CMOV_V4F32:
-  case X86::NEW_CMOV_V2F64:
-  case X86::NEW_CMOV_V2I64: {
+  case X86::CMOV_V2I64: {
     // To "insert" a SELECT_CC instruction, we actually have to insert the
     // diamond control-flow pattern.  The incoming instruction knows the
     // destination vreg to set, the condition code register to branch on, the
@@ -5065,7 +4881,6 @@ void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
   switch (Opc) {
   default: break;
   case X86ISD::SETCC:
-  case X86ISD::SETCC_NEW:
     KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
     break;
   }
diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h
index 6e70a0b3fa..9af46801d2 100644
--- a/lib/Target/X86/X86ISelLowering.h
+++ b/lib/Target/X86/X86ISelLowering.h
@@ -117,26 +117,22 @@ namespace llvm {
 
       /// X86 compare and logical compare instructions.
       CMP, COMI, UCOMI,
-      CMP_NEW, COMI_NEW, UCOMI_NEW,
 
       /// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
       /// operand produced by a CMP instruction.
       SETCC,
-      SETCC_NEW,
 
       /// X86 conditional moves. Operand 1 and operand 2 are the two values
       /// to select from (operand 1 is a R/W operand). Operand 3 is the
       /// condition code, and operand 4 is the flag operand produced by a CMP
       /// or TEST instruction. It also writes a flag result.
       CMOV,
-      CMOV_NEW,
 
       /// X86 conditional branches. Operand 1 is the chain operand, operand 2
       /// is the block to branch if condition is true, operand 3 is the
       /// condition code, and operand 4 is the flag operand produced by a CMP
       /// or TEST instruction.
       BRCOND,
-      BRCOND_NEW,
 
       /// Return with a flag operand. Operand 1 is the chain operand, operand
       /// 2 is the number of bytes of stack to pop.
@@ -430,12 +426,9 @@ namespace llvm {
     SDOperand LowerFABS(SDOperand Op, SelectionDAG &DAG);
     SDOperand LowerFNEG(SDOperand Op, SelectionDAG &DAG);
     SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG);
-    SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG, SDOperand Chain);
-    SDOperand LowerSETCC_New(SDOperand Op, SelectionDAG &DAG);
+    SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG);
     SDOperand LowerSELECT(SDOperand Op, SelectionDAG &DAG);
-    SDOperand LowerSELECT_New(SDOperand Op, SelectionDAG &DAG);
     SDOperand LowerBRCOND(SDOperand Op, SelectionDAG &DAG);
-    SDOperand LowerBRCOND_New(SDOperand Op, SelectionDAG &DAG);
     SDOperand LowerMEMSET(SDOperand Op, SelectionDAG &DAG);
     SDOperand LowerMEMCPYInline(SDOperand Dest, SDOperand Source,
                                 SDOperand Chain, unsigned Size, unsigned Align,
diff --git a/lib/Target/X86/X86InstrFPStack.td b/lib/Target/X86/X86InstrFPStack.td
index ec6373262e..a26a4ffc71 100644
--- a/lib/Target/X86/X86InstrFPStack.td
+++ b/lib/Target/X86/X86InstrFPStack.td
@@ -299,17 +299,20 @@ def TST_F  : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9;
 
 // Floating point cmovs.
 multiclass FPCMov<PatLeaf cc> {
-  def _Fp32  : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), CondMovFP,
+  def _Fp32  : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2),
+                       CondMovFP,
                      [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2,
-                                        cc))]>;
-  def _Fp64  : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), CondMovFP,
+                                        cc, EFLAGS))]>;
+  def _Fp64  : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2),
+                       CondMovFP,
                      [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2,
-                                        cc))]>;
-  def _Fp80  : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), CondMovFP,
+                                        cc, EFLAGS))]>;
+  def _Fp80  : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2),
+                     CondMovFP,
                      [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2,
-                                        cc))]>;
+                                        cc, EFLAGS))]>;
 }
-let isTwoAddress = 1 in {
+let Uses = [EFLAGS], isTwoAddress = 1 in {
 defm CMOVB  : FPCMov<X86_COND_B>;
 defm CMOVBE : FPCMov<X86_COND_BE>;
 defm CMOVE  : FPCMov<X86_COND_E>;
@@ -320,31 +323,6 @@ defm CMOVNE : FPCMov<X86_COND_NE>;
 defm CMOVNP : FPCMov<X86_COND_NP>;
 }
 
-multiclass NEW_FPCMov<PatLeaf cc> {
-  def _Fp32  : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2),
-                       CondMovFP,
-                     [(set RFP32:$dst, (X86cmov_new RFP32:$src1, RFP32:$src2,
-                                        cc, EFLAGS))]>;
-  def _Fp64  : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2),
-                       CondMovFP,
-                     [(set RFP64:$dst, (X86cmov_new RFP64:$src1, RFP64:$src2,
-                                        cc, EFLAGS))]>;
-  def _Fp80  : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2),
-                     CondMovFP,
-                     [(set RFP80:$dst, (X86cmov_new RFP80:$src1, RFP80:$src2,
-                                        cc, EFLAGS))]>;
-}
-let Uses = [EFLAGS], isTwoAddress = 1 in {
-defm NEW_CMOVB  : NEW_FPCMov<X86_COND_B>;
-defm NEW_CMOVBE : NEW_FPCMov<X86_COND_BE>;
-defm NEW_CMOVE  : NEW_FPCMov<X86_COND_E>;
-defm NEW_CMOVP  : NEW_FPCMov<X86_COND_P>;
-defm NEW_CMOVNB : NEW_FPCMov<X86_COND_AE>;
-defm NEW_CMOVNBE: NEW_FPCMov<X86_COND_A>;
-defm NEW_CMOVNE : NEW_FPCMov<X86_COND_NE>;
-defm NEW_CMOVNP : NEW_FPCMov<X86_COND_NP>;
-}
-
 // These are not factored because there's no clean way to pass DA/DB.
 def CMOVB_F  : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
                   "fcmovb\t{$op, %st(0)|%ST(0), $op}">, DA;
@@ -507,30 +485,17 @@ let Defs = [EFLAGS] in {
 def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
                   []>;  // FPSW = cmp ST(0) with ST(i)
 def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
-                  [(X86cmp RFP32:$lhs, RFP32:$rhs)]>; // CC = ST(0) cmp ST(i)
+                  [(X86cmp RFP32:$lhs, RFP32:$rhs),
+                   (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
 def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
                   []>;  // FPSW = cmp ST(0) with ST(i)
 def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
-                  [(X86cmp RFP64:$lhs, RFP64:$rhs)]>; // CC = ST(0) cmp ST(i)
+                  [(X86cmp RFP64:$lhs, RFP64:$rhs),
+                   (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
 def UCOM_Fpr80 : FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
                   []>;  // FPSW = cmp ST(0) with ST(i)
 def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
-                  [(X86cmp RFP80:$lhs, RFP80:$rhs)]>; // CC = ST(0) cmp ST(i)
-
-def NEW_UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
-                  []>;  // FPSW = cmp ST(0) with ST(i)
-def NEW_UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
-                  [(X86cmp_new RFP32:$lhs, RFP32:$rhs),
-                   (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
-def NEW_UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
-                  []>;  // FPSW = cmp ST(0) with ST(i)
-def NEW_UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
-                  [(X86cmp_new RFP64:$lhs, RFP64:$rhs),
-                   (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
-def NEW_UCOM_Fpr80 : FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
-                  []>;  // FPSW = cmp ST(0) with ST(i)
-def NEW_UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
-                  [(X86cmp_new RFP80:$lhs, RFP80:$rhs),
+                  [(X86cmp RFP80:$lhs, RFP80:$rhs),
                    (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
 }
 
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index e510369399..59b8116812 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -386,68 +386,28 @@ static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
   case X86::JNP: return X86::COND_NP;
   case X86::JO:  return X86::COND_O;
   case X86::JNO: return X86::COND_NO;
-  // TEMPORARY
-  case X86::NEW_JE:  return X86::COND_E;
-  case X86::NEW_JNE: return X86::COND_NE;
-  case X86::NEW_JL:  return X86::COND_L;
-  case X86::NEW_JLE: return X86::COND_LE;
-  case X86::NEW_JG:  return X86::COND_G;
-  case X86::NEW_JGE: return X86::COND_GE;
-  case X86::NEW_JB:  return X86::COND_B;
-  case X86::NEW_JBE: return X86::COND_BE;
-  case X86::NEW_JA:  return X86::COND_A;
-  case X86::NEW_JAE: return X86::COND_AE;
-  case X86::NEW_JS:  return X86::COND_S;
-  case X86::NEW_JNS: return X86::COND_NS;
-  case X86::NEW_JP:  return X86::COND_P;
-  case X86::NEW_JNP: return X86::COND_NP;
-  case X86::NEW_JO:  return X86::COND_O;
-  case X86::NEW_JNO: return X86::COND_NO;
-
   }
 }
 
 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
-  if (!NewCCModeling) {
-    switch (CC) {
-    default: assert(0 && "Illegal condition code!");
-    case X86::COND_E:  return X86::JE;
-    case X86::COND_NE: return X86::JNE;
-    case X86::COND_L:  return X86::JL;
-    case X86::COND_LE: return X86::JLE;
-    case X86::COND_G:  return X86::JG;
-    case X86::COND_GE: return X86::JGE;
-    case X86::COND_B:  return X86::JB;
-    case X86::COND_BE: return X86::JBE;
-    case X86::COND_A:  return X86::JA;
-    case X86::COND_AE: return X86::JAE;
-    case X86::COND_S:  return X86::JS;
-    case X86::COND_NS: return X86::JNS;
-    case X86::COND_P:  return X86::JP;
-    case X86::COND_NP: return X86::JNP;
-    case X86::COND_O:  return X86::JO;
-    case X86::COND_NO: return X86::JNO;
-    }
-  }
-
   switch (CC) {
   default: assert(0 && "Illegal condition code!");
-  case X86::COND_E:  return X86::NEW_JE;
-  case X86::COND_NE: return X86::NEW_JNE;
-  case X86::COND_L:  return X86::NEW_JL;
-  case X86::COND_LE: return X86::NEW_JLE;
-  case X86::COND_G:  return X86::NEW_JG;
-  case X86::COND_GE: return X86::NEW_JGE;
-  case X86::COND_B:  return X86::NEW_JB;
-  case X86::COND_BE: return X86::NEW_JBE;
-  case X86::COND_A:  return X86::NEW_JA;
-  case X86::COND_AE: return X86::NEW_JAE;
-  case X86::COND_S:  return X86::NEW_JS;
-  case X86::COND_NS: return X86::NEW_JNS;
-  case X86::COND_P:  return X86::NEW_JP;
-  case X86::COND_NP: return X86::NEW_JNP;
-  case X86::COND_O:  return X86::NEW_JO;
-  case X86::COND_NO: return X86::NEW_JNO;
+  case X86::COND_E:  return X86::JE;
+  case X86::COND_NE: return X86::JNE;
+  case X86::COND_L:  return X86::JL;
+  case X86::COND_LE: return X86::JLE;
+  case X86::COND_G:  return X86::JG;
+  case X86::COND_GE: return X86::JGE;
+  case X86::COND_B:  return X86::JB;
+  case X86::COND_BE: return X86::JBE;
+  case X86::COND_A:  return X86::JA;
+  case X86::COND_AE: return X86::JAE;
+  case X86::COND_S:  return X86::JS;
+  case X86::COND_NS: return X86::JNS;
+  case X86::COND_P:  return X86::JP;
+  case X86::COND_NP: return X86::JNP;
+  case X86::COND_O:  return X86::JO;
+  case X86::COND_NO: return X86::JNO;
   }
 }
 
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 86e102e1d1..1a0fab3b86 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -23,22 +23,15 @@ def SDTIntShiftDOp: SDTypeProfile<1, 3,
 
 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
 
-def SDTX86Cmov    : SDTypeProfile<1, 3,
-                                  [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
-                                   SDTCisVT<3, i8>]>;
-def SDTX86Cmov_NEW : SDTypeProfile<1, 4,
+def SDTX86Cmov    : SDTypeProfile<1, 4,
                                   [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
                                    SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
 
-def SDTX86BrCond  : SDTypeProfile<0, 2,
-                                  [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>;
-def SDTX86BrCond_NEW  : SDTypeProfile<0, 3,
+def SDTX86BrCond  : SDTypeProfile<0, 3,
                                   [SDTCisVT<0, OtherVT>,
                                    SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
 
-def SDTX86SetCC   : SDTypeProfile<1, 1,
-                                  [SDTCisVT<0, i8>, SDTCisVT<1, i8>]>;
-def SDTX86SetCC_NEW   : SDTypeProfile<1, 2,
+def SDTX86SetCC   : SDTypeProfile<1, 2,
                                   [SDTCisVT<0, i8>,
                                    SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
 
@@ -65,20 +58,12 @@ def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
 def X86shld    : SDNode<"X86ISD::SHLD",     SDTIntShiftDOp>;
 def X86shrd    : SDNode<"X86ISD::SHRD",     SDTIntShiftDOp>;
 
-def X86cmp     : SDNode<"X86ISD::CMP" ,     SDTX86CmpTest,
-                        [SDNPHasChain, SDNPOutFlag]>;
-def X86cmp_new : SDNode<"X86ISD::CMP_NEW" ,     SDTX86CmpTest>;
+def X86cmp     : SDNode<"X86ISD::CMP" ,     SDTX86CmpTest>;
 
-def X86cmov    : SDNode<"X86ISD::CMOV",     SDTX86Cmov,
-                        [SDNPInFlag, SDNPOutFlag]>;
-def X86cmov_new: SDNode<"X86ISD::CMOV_NEW",     SDTX86Cmov_NEW>;
+def X86cmov    : SDNode<"X86ISD::CMOV",     SDTX86Cmov>;
 def X86brcond  : SDNode<"X86ISD::BRCOND",   SDTX86BrCond,
-                        [SDNPHasChain, SDNPInFlag]>;
-def X86brcond_new  : SDNode<"X86ISD::BRCOND_NEW",   SDTX86BrCond_NEW,
                         [SDNPHasChain]>;
-def X86setcc   : SDNode<"X86ISD::SETCC",    SDTX86SetCC,
-                        [SDNPInFlag, SDNPOutFlag]>;
-def X86setcc_new : SDNode<"X86ISD::SETCC_NEW",    SDTX86SetCC_NEW>;
+def X86setcc   : SDNode<"X86ISD::SETCC",    SDTX86SetCC>;
 
 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,