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authorChris Lattner <sabre@nondot.org>2005-01-30 16:32:48 +0000
committerChris Lattner <sabre@nondot.org>2005-01-30 16:32:48 +0000
commitd7b59d0181ba862dc7d1a3a4b1ae114e9bc6958a (patch)
treecfc4043152cf0362ce43fea3475a146990b19f7f /lib
parent684f22989597ac00f493eca91be798ad0cb401f5 (diff)
Fix warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19933 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/Alpha/AlphaISelPattern.cpp2
-rw-r--r--lib/Target/Alpha/AlphaRegisterInfo.cpp2
2 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index e49fdfbee6..f654845884 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -1149,7 +1149,7 @@ void ISel::Select(SDOperand N) {
Tmp2 = SelectExpr(N.getOperand(2));
switch (StoredTy) {
- default: Node->dump(); assert(0 && "Unhandled Type"); break;
+ default: Node->dump(); assert(0 && "Unhandled Type");
case MVT::i1: //FIXME: DAG does not promote this load
case MVT::i8: Opc = Alpha::STB; break;
case MVT::i16: Opc = Alpha::STW; break;
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index a35c210d20..7e6c5d38f3 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -108,7 +108,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
Amount = (Amount+Align-1)/Align*Align;
- MachineInstr *New;
+// MachineInstr *New;
// if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
// New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
// .addZImm(Amount);