Add support for the "Y" register, used by MUL & DIV.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12734 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 18 insertions, 0 deletions

diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td
index 09246c0a41..6d2496dbcb 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.td
+++ b/lib/Target/Sparc/SparcRegisterInfo.td
@@ -24,6 +24,15 @@ class Rf<bits<5> num> : Register {
 class Rd<bits<5> num> : Register {
   field bits<5> Num = num;
 }
+// Rs - Special "ancillary state registers"
+class Rs<bits<5> num> : Register {
+  field bits<5> Num = num;
+}
+
+// Special register used for multiplies and divides
+let Namespace = "V8" in {
+  def Y : Rs<0>;
+}
 
 let Namespace = "V8" in {
   def G0 : Ri< 0>;    def G1 : Ri< 1>;    def G2 : Ri< 2>;    def G3 : Ri< 3>;
diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.td b/lib/Target/SparcV8/SparcV8RegisterInfo.td
index 09246c0a41..6d2496dbcb 100644
--- a/lib/Target/SparcV8/SparcV8RegisterInfo.td
+++ b/lib/Target/SparcV8/SparcV8RegisterInfo.td
@@ -24,6 +24,15 @@ class Rf<bits<5> num> : Register {
 class Rd<bits<5> num> : Register {
   field bits<5> Num = num;
 }
+// Rs - Special "ancillary state registers"
+class Rs<bits<5> num> : Register {
+  field bits<5> Num = num;
+}
+
+// Special register used for multiplies and divides
+let Namespace = "V8" in {
+  def Y : Rs<0>;
+}
 
 let Namespace = "V8" in {
   def G0 : Ri< 0>;    def G1 : Ri< 1>;    def G2 : Ri< 2>;    def G3 : Ri< 3>;