diff options
| author | Dan Gohman <gohman@apple.com> | 2008-04-16 02:32:24 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2008-04-16 02:32:24 +0000 |
| commit | 171c11ec93d74c71f7e4f8bfb9c9cd5971214b53 (patch) | |
| tree | 65821acd32435f1829eae55dce15522acd044695 /lib | |
| parent | bcda285fcc98129ce48c4eda72a7f3595c7685ec (diff) | |
Add support for the form of the SSE41 extractps instruction that
puts its result in a 32-bit GPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49762 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 6 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 5 |
2 files changed, 6 insertions, 5 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index d8eaee71c8..69acf1a018 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -3833,11 +3833,13 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDOperand Op, } else if (VT == MVT::f32) { // EXTRACTPS outputs to a GPR32 register which will require a movd to copy // the result back to FR32 register. It's only worth matching if the - // result has a single use which is a store. + // result has a single use which is a store or a bitcast to i32. if (!Op.hasOneUse()) return SDOperand(); SDNode *User = Op.Val->use_begin()->getUser(); - if (User->getOpcode() != ISD::STORE) + if (User->getOpcode() != ISD::STORE && + (User->getOpcode() != ISD::BIT_CONVERT || + User->getValueType(0) != MVT::i32)) return SDOperand(); SDOperand Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)), diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 442847cda8..982b0dc6df 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -3387,13 +3387,12 @@ defm PEXTRD : SS41I_extract32<0x16, "pextrd">; /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory /// destination multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> { - // Not worth matching to rr form of extractps since the result is in GPR32. def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), - [/*(set GR32:$dst, - (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))*/]>, + [(set GR32:$dst, + (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>, OpSize; def mr : SS4AIi8<opc, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2), |