diff options
| author | Scott Michel <scottm@aero.org> | 2007-12-19 20:15:47 +0000 |
|---|---|---|
| committer | Scott Michel <scottm@aero.org> | 2007-12-19 20:15:47 +0000 |
| commit | 170783a5fc13fff2878d4d347d8bd9096f2ef8d9 (patch) | |
| tree | 2080350b2d374eb834db51b16cf185f8384cd5b2 /lib | |
| parent | f021f8a5acd5ed9d4651fd9b07edbe6b6c38635c (diff) | |
Two more test cases: or_ops.ll (arithmetic or operations) and vecinsert.ll
(vector insertions)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45216 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/CellSPU/SPUISelLowering.cpp | 7 | ||||
| -rw-r--r-- | lib/Target/CellSPU/SPUInstrInfo.cpp | 4 |
2 files changed, 5 insertions, 6 deletions
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 253fafb8e9..7d22187751 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -880,13 +880,12 @@ LowerConstantFP(SDOperand Op, SelectionDAG &DAG) { assert((FP != 0) && "LowerConstantFP: Node is not ConstantFPSDNode"); - const APFloat &apf = FP->getValueAPF(); - if (VT == MVT::f32) { + float targetConst = FP->getValueAPF().convertToFloat(); return DAG.getNode(SPUISD::SFPConstant, VT, - DAG.getTargetConstantFP(apf.convertToFloat(), VT)); + DAG.getTargetConstantFP(targetConst, VT)); } else if (VT == MVT::f64) { - uint64_t dbits = DoubleToBits(apf.convertToDouble()); + uint64_t dbits = DoubleToBits(FP->getValueAPF().convertToDouble()); return DAG.getNode(ISD::BIT_CONVERT, VT, LowerConstant(DAG.getConstant(dbits, MVT::i64), DAG)); } diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp index efd45f56dc..5c2bd52d50 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -98,13 +98,13 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI, destReg = MI.getOperand(0).getReg(); return true; #endif - // case SPU::ORv16i8_i8: + case SPU::ORv16i8_i8: case SPU::ORv8i16_i16: case SPU::ORv4i32_i32: case SPU::ORv2i64_i64: case SPU::ORv4f32_f32: case SPU::ORv2f64_f64: - // case SPU::ORi8_v16i8: + case SPU::ORi8_v16i8: case SPU::ORi16_v8i16: case SPU::ORi32_v4i32: case SPU::ORi64_v2i64: |