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authorShuxin Yang <shuxin.llvm@gmail.com>2012-12-04 03:28:32 +0000
committerShuxin Yang <shuxin.llvm@gmail.com>2012-12-04 03:28:32 +0000
commitbba3eb054a4e0e052cdeff22e678c52c4e59f07e (patch)
tree5d2f2bdc5691d86fd14c6736477f1e32763fa0c2 /lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
parentb715b205a41dc53942acbcfbfdbdce6bdaf9a4aa (diff)
rdar://12329730 (2nd part, revised)
The type of shirt-right (logical or arithemetic) should remain unchanged when transforming "X << C1 >> C2" into "X << (C1-C2)" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169209 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp')
-rw-r--r--lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index c65076e883..c832ca5644 100644
--- a/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -876,7 +876,8 @@ Value *InstCombiner::SimplifyShrShlDemandedBits(Instruction *Shr,
New->setHasNoUnsignedWrap(Orig->hasNoUnsignedWrap());
} else {
Constant *Amt = ConstantInt::get(VarX->getType(), ShrAmt - ShlAmt);
- New = BinaryOperator::CreateLShr(VarX, Amt);
+ New = isLshr ? BinaryOperator::CreateLShr(VarX, Amt) :
+ BinaryOperator::CreateAShr(VarX, Amt);
}
return InsertNewInstWith(New, *Shl);