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| author | Chris Lattner <sabre@nondot.org> | 2011-02-10 05:09:34 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2011-02-10 05:09:34 +0000 |
| commit | a81556fb52e39e3f6cde0c11c1acd2bdf8a560a2 (patch) | |
| tree | 2a94b97bd825bc7bd08c100423b9dd93b32d17e2 /lib/Transforms/InstCombine/InstCombineAddSub.cpp | |
| parent | 4d96c638af0458f4de637998da942a5e166d6ea5 (diff) | |
teach SimplifyDemandedBits that exact shifts demand the bits they
are shifting out since they do require them to be zeros. Similarly
for NUW/NSW bits of shl
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125263 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Transforms/InstCombine/InstCombineAddSub.cpp')
0 files changed, 0 insertions, 0 deletions