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authorChris Lattner <sabre@nondot.org>2010-12-15 05:51:39 +0000
committerChris Lattner <sabre@nondot.org>2010-12-15 05:51:39 +0000
commit1a0fbe2cf438ac2788df669284293789681424e1 (patch)
treeea11bc8217c895545c74d3f9478ea7ce26315395 /lib/Transforms/InstCombine/InstCombineAddSub.cpp
parentba3c8155704e5e2ac24b5069c32bca359b0738ed (diff)
when transforming a MULHS into a wider MUL, there is no need to SRA the
result, the top bits are truncated off anyway, just use SRL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121846 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Transforms/InstCombine/InstCombineAddSub.cpp')
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