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authorChristian Konig <christian.koenig@amd.com>2013-02-26 17:52:36 +0000
committerChristian Konig <christian.koenig@amd.com>2013-02-26 17:52:36 +0000
commitb37afdcf3fa41596ab1f70eef915a8ade68ccc24 (patch)
treed5a61a259ee5073e3c5d46a1236ccb0b51981a65 /lib/Target
parentb3d1eaded7d7a874bbda2b0d322df7389c724bfc (diff)
R600/SI: swap operands if it helps folding
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176103 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r--lib/Target/R600/SIISelLowering.cpp16
1 files changed, 15 insertions, 1 deletions
diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp
index bf1f3bf750..da30c078c7 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -545,8 +545,22 @@ SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
// Is this a VSrc or SSrc operand ?
unsigned RegClass = Desc->OpInfo[Op].RegClass;
- if (!isVSrc(RegClass) && !isSSrc(RegClass))
+ if (!isVSrc(RegClass) && !isSSrc(RegClass)) {
+
+ if (i == 1 && Desc->isCommutable() &&
+ fitsRegClass(DAG, Ops[0], RegClass) &&
+ foldImm(Ops[1], Immediate, ScalarSlotUsed)) {
+
+ assert(isVSrc(Desc->OpInfo[NumDefs].RegClass) ||
+ isSSrc(Desc->OpInfo[NumDefs].RegClass));
+
+ // Swap commutable operands
+ SDValue Tmp = Ops[1];
+ Ops[1] = Ops[0];
+ Ops[0] = Tmp;
+ }
continue;
+ }
// Try to fold the immediates
if (!foldImm(Ops[i], Immediate, ScalarSlotUsed)) {