Change interface of MachineOperand as follows:

    a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
    b) add isUse(), isDef()
    c) rename opHiBits32() to isHiBits32(),
              opLoBits32() to isLoBits32(),
              opHiBits64() to isHiBits64(),
              opLoBits64() to isLoBits64().

This results to much more readable code, for example compare
"op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used
very often in the code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10461 91177308-0d34-0410-b5e6-96231b3b80d8

12 files changed, 58 insertions, 72 deletions

diff --git a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
index 3a8088043b..2dafe62c72 100644
--- a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
+++ b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
@@ -342,8 +342,8 @@ void SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
       unsigned int opNum   = regRefVec[i].second;
       const MachineOperand& mop =
         node->getMachineInstr()->getExplOrImplOperand(opNum);
-      bool isDef = mop.opIsDefOnly();
-      bool isDefAndUse = mop.opIsDefAndUse();
+      bool isDef = mop.isDef() && !mop.isUse();
+      bool isDefAndUse = mop.isDef() && mop.isUse();
           
       for (unsigned p=0; p < i; ++p) {
         SchedGraphNode* prevNode = regRefVec[p].first;
@@ -351,8 +351,8 @@ void SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
           unsigned int prevOpNum = regRefVec[p].second;
           const MachineOperand& prevMop =
             prevNode->getMachineInstr()->getExplOrImplOperand(prevOpNum);
-          bool prevIsDef = prevMop.opIsDefOnly();
-          bool prevIsDefAndUse = prevMop.opIsDefAndUse();
+          bool prevIsDef = prevMop.isDef() && !prevMop.isUse();
+          bool prevIsDefAndUse = prevMop.isDef() && prevMop.isUse();
           if (isDef) {
             if (prevIsDef)
               new SchedGraphEdge(prevNode, node, regNum,
@@ -381,10 +381,8 @@ void SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
 				  const RefVec& defVec,
 				  const Value* defValue,
 				  bool  refNodeIsDef,
-				  bool  refNodeIsDefAndUse,
+				  bool  refNodeIsUse,
 				  const TargetMachine& target) {
-  bool refNodeIsUse = !refNodeIsDef || refNodeIsDefAndUse;
-  
   // Add true or output dep edges from all def nodes before refNode in BB.
   // Add anti or output dep edges to all def nodes after refNode.
   for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I) {
@@ -393,7 +391,7 @@ void SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
     
     if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB()) {
       // (*).first is before refNode
-      if (refNodeIsDef)
+      if (refNodeIsDef && !refNodeIsUse)
         (void) new SchedGraphEdge((*I).first, refNode, defValue,
                                   SchedGraphEdge::OutputDep);
       if (refNodeIsUse)
@@ -401,7 +399,7 @@ void SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
                                   SchedGraphEdge::TrueDep);
     } else {
       // (*).first is after refNode
-      if (refNodeIsDef)
+      if (refNodeIsDef && !refNodeIsUse)
         (void) new SchedGraphEdge(refNode, (*I).first, defValue,
                                   SchedGraphEdge::OutputDep);
       if (refNodeIsUse)
@@ -429,8 +427,8 @@ void SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
         ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
         if (I != valueToDefVecMap.end())
           addEdgesForValue(node, I->second, srcI,
-                           MI.getOperand(i).opIsDefOnly(),
-                           MI.getOperand(i).opIsDefAndUse(), target);
+                           MI.getOperand(i).isDef(), MI.getOperand(i).isUse(),
+                           target);
       }
       break;
       
@@ -454,13 +452,13 @@ void SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
   // value of a Ret instruction.
   // 
   for (unsigned i=0, N=MI.getNumImplicitRefs(); i < N; ++i)
-    if (MI.getImplicitOp(i).opIsUse() || MI.getImplicitOp(i).opIsDefAndUse())
+    if (MI.getImplicitOp(i).isUse())
       if (const Value* srcI = MI.getImplicitRef(i)) {
         ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
         if (I != valueToDefVecMap.end())
           addEdgesForValue(node, I->second, srcI,
-                           MI.getImplicitOp(i).opIsDefOnly(),
-                           MI.getImplicitOp(i).opIsDefAndUse(), target);
+                           MI.getImplicitOp(i).isDef(),
+                           MI.getImplicitOp(i).isUse(), target);
       }
 }
 
@@ -512,8 +510,7 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
     }
     
     // ignore all other non-def operands
-    if (!MI.getOperand(i).opIsDefOnly() &&
-        !MI.getOperand(i).opIsDefAndUse())
+    if (!MI.getOperand(i).isDef())
       continue;
       
     // We must be defining a value.
@@ -539,10 +536,10 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
       continue;                     // nothing more to do
     }
 
-    if (mop.opIsDefOnly() || mop.opIsDefAndUse()) {
+    if (mop.isDef()) {
       assert(MI.getImplicitRef(i) != NULL && "Null value being defined?");
-      valueToDefVecMap[MI.getImplicitRef(i)].push_back(std::make_pair(node,
-                                                                          -i)); 
+      valueToDefVecMap[MI.getImplicitRef(i)].push_back(
+        std::make_pair(node, -i)); 
     }
   }
 }
diff --git a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
index 73e5480d12..a58aed90be 100644
--- a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
+++ b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
@@ -178,8 +178,8 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
 
         // Bit-selection flags indicate an instruction that is extracting
         // bits from its operand so ignore this even if it is a big constant.
-        if (mop.opHiBits32() || mop.opLoBits32() ||
-            mop.opHiBits64() || mop.opLoBits64())
+        if (mop.isHiBits32() || mop.isLoBits32() ||
+            mop.isHiBits64() || mop.isLoBits64())
           continue;
 
         opType = ChooseRegOrImmed(mop.getImmedValue(), isSigned,
diff --git a/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp b/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp
index 758f1b1539..270fbbd830 100644
--- a/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp
+++ b/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp
@@ -52,12 +52,12 @@ void BBLiveVar::calcDefUseSets() {
     // iterate over  MI operands to find defs
     for (MachineInstr::const_val_op_iterator OpI = MI->begin(), OpE = MI->end();
          OpI != OpE; ++OpI)
-      if (OpI.isDefOnly() || OpI.isDefAndUse()) // add to Defs if this operand is a def
+      if (OpI.isDef()) // add to Defs if this operand is a def
 	addDef(*OpI);
 
     // do for implicit operands as well
     for (unsigned i = 0; i < MI->getNumImplicitRefs(); ++i)
-      if (MI->getImplicitOp(i).opIsDefOnly() || MI->getImplicitOp(i).opIsDefAndUse())
+      if (MI->getImplicitOp(i).isDef())
 	addDef(MI->getImplicitRef(i));
     
     // iterate over MI operands to find uses
@@ -68,8 +68,7 @@ void BBLiveVar::calcDefUseSets() {
       if (isa<BasicBlock>(Op))
 	continue;             // don't process labels
 
-      if (OpI.isUseOnly() || OpI.isDefAndUse()) {
-                                // add to Uses only if this operand is a use
+      if (OpI.isUse()) { // add to Uses only if this operand is a use
         //
         // *** WARNING: The following code for handling dummy PHI machine
         //     instructions is untested.  The previous code was broken and I
@@ -104,7 +103,7 @@ void BBLiveVar::calcDefUseSets() {
       if (Op->getType() == Type::LabelTy)             // don't process labels
 	continue;
 
-      if (MI->getImplicitOp(i).opIsUse() || MI->getImplicitOp(i).opIsDefAndUse())
+      if (MI->getImplicitOp(i).isUse())
 	addUse(Op);
     }
   } // for all machine instructions
diff --git a/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp b/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp
index 8f0e31811a..e342760f72 100644
--- a/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp
+++ b/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp
@@ -235,14 +235,13 @@ FunctionLiveVarInfo::getLiveVarSetAfterMInst(const MachineInstr *MI,
 static void applyTranferFuncForMInst(ValueSet &LVS, const MachineInstr *MInst) {
   for (MachineInstr::const_val_op_iterator OpI = MInst->begin(),
          OpE = MInst->end(); OpI != OpE; ++OpI) {
-    if (OpI.isDefOnly() || OpI.isDefAndUse()) // kill if this operand is a def
+    if (OpI.isDef())                          // kill if this operand is a def
       LVS.erase(*OpI);                        // this definition kills any uses
   }
 
   // do for implicit operands as well
   for (unsigned i=0; i < MInst->getNumImplicitRefs(); ++i) {
-    if (MInst->getImplicitOp(i).opIsDefOnly() ||
-        MInst->getImplicitOp(i).opIsDefAndUse())
+    if (MInst->getImplicitOp(i).isDef())
       LVS.erase(MInst->getImplicitRef(i));
   }
 
@@ -250,14 +249,13 @@ static void applyTranferFuncForMInst(ValueSet &LVS, const MachineInstr *MInst) {
          OpE = MInst->end(); OpI != OpE; ++OpI) {
     if (!isa<BasicBlock>(*OpI))      // don't process labels
       // add only if this operand is a use
-      if (!OpI.isDefOnly() || OpI.isDefAndUse() )
+      if (OpI.isUse())
         LVS.insert(*OpI);            // An operand is a use - so add to use set
   }
 
   // do for implicit operands as well
   for (unsigned i = 0, e = MInst->getNumImplicitRefs(); i != e; ++i)
-    if (MInst->getImplicitOp(i).opIsUse() ||
-        MInst->getImplicitOp(i).opIsDefAndUse())
+    if (MInst->getImplicitOp(i).isUse())
       LVS.insert(MInst->getImplicitRef(i));
 }
 
diff --git a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
index 9fd04d2b0e..380680448d 100644
--- a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
+++ b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
@@ -184,7 +184,7 @@ void LiveRangeInfo::constructLiveRanges() {
       // for each operand that is defined by the instruction
       for (MachineInstr::val_op_iterator OpI = MInst->begin(),
              OpE = MInst->end(); OpI != OpE; ++OpI)
-	if (OpI.isDefOnly() || OpI.isDefAndUse()) {     
+	if (OpI.isDef()) {     
 	  const Value *Def = *OpI;
           bool isCC = (OpI.getMachineOperand().getType()
                        == MachineOperand::MO_CCRegister);
@@ -203,8 +203,7 @@ void LiveRangeInfo::constructLiveRanges() {
       // iterate over implicit MI operands and create a new LR
       // for each operand that is defined by the instruction
       for (unsigned i = 0; i < MInst->getNumImplicitRefs(); ++i) 
-	if (MInst->getImplicitOp(i).opIsDefOnly() ||
-            MInst->getImplicitOp(i).opIsDefAndUse()) {     
+	if (MInst->getImplicitOp(i).isDef()) {
 	  const Value *Def = MInst->getImplicitRef(i);
           LiveRange* LR = createOrAddToLiveRange(Def, /*isCC*/ false);
 
@@ -342,7 +341,7 @@ void LiveRangeInfo::coalesceLRs()
       // iterate over  MI operands to find defs
       for(MachineInstr::const_val_op_iterator DefI = MI->begin(),
             DefE = MI->end(); DefI != DefE; ++DefI) {
-	if (DefI.isDefOnly() || DefI.isDefAndUse()) { // this operand is modified
+	if (DefI.isDef()) { // this operand is modified
 	  LiveRange *LROfDef = getLiveRangeForValue( *DefI );
 	  RegClass *RCOfDef = LROfDef->getRegClass();
 
diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
index 332ae9524c..a9a5f3d7fe 100644
--- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
@@ -250,7 +250,7 @@ void PhyRegAlloc::buildInterferenceGraphs() {
       // iterate over all MI operands to find defs
       for (MachineInstr::const_val_op_iterator OpI = MInst->begin(),
              OpE = MInst->end(); OpI != OpE; ++OpI) {
-       	if (OpI.isDefOnly() || OpI.isDefAndUse()) // create a new LR since def
+       	if (OpI.isDef()) // create a new LR since def
 	  addInterference(*OpI, &LVSetAI, isCallInst);
 
 	// Calculate the spill cost of each live range
@@ -269,8 +269,7 @@ void PhyRegAlloc::buildInterferenceGraphs() {
       // instr (currently, only calls have this).
       unsigned NumOfImpRefs =  MInst->getNumImplicitRefs();
       for (unsigned z=0; z < NumOfImpRefs; z++) 
-        if (MInst->getImplicitOp(z).opIsDefOnly() ||
-	    MInst->getImplicitOp(z).opIsDefAndUse())
+        if (MInst->getImplicitOp(z).isDef())
 	  addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst );
 
     } // for all machine instructions in BB
@@ -295,7 +294,7 @@ void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
   for (MachineInstr::const_val_op_iterator It1 = MInst->begin(),
          ItE = MInst->end(); It1 != ItE; ++It1) {
     const LiveRange *LROfOp1 = LRI->getLiveRangeForValue(*It1); 
-    assert((LROfOp1 || !It1.isUseOnly())&&"No LR for Def in PSEUDO insruction");
+    assert((LROfOp1 || It1.isDef()) && "No LR for Def in PSEUDO insruction");
 
     MachineInstr::const_val_op_iterator It2 = It1;
     for (++It2; It2 != ItE; ++It2) {
@@ -645,8 +644,8 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
 	 "Return value of a ret must be handled elsewhere");
 
   MachineOperand& Op = MInst->getOperand(OpNum);
-  bool isDef =  Op.opIsDefOnly();
-  bool isDefAndUse = Op.opIsDefAndUse();
+  bool isDef =  Op.isDef();
+  bool isUse = Op.isUse();
   unsigned RegType = MRI.getRegTypeForLR(LR);
   int SpillOff = LR->getSpillOffFromFP();
   RegClass *RC = LR->getRegClass();
@@ -699,7 +698,7 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
       assert(scratchReg != MRI.getInvalidRegNum());
     }
   
-  if (!isDef || isDefAndUse) {
+  if (isUse) {
     // for a USE, we have to load the value of LR from stack to a TmpReg
     // and use the TmpReg as one operand of instruction
     
@@ -712,7 +711,7 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
     AdIMid.clear();
   }
   
-  if (isDef || isDefAndUse) {   // if this is a Def
+  if (isDef) {   // if this is a Def
     // for a DEF, we have to store the value produced by this instruction
     // on the stack position allocated for this LR
     
diff --git a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
index 1e75acabbe..ec190ca7cf 100644
--- a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
+++ b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
@@ -735,13 +735,13 @@ SparcAsmPrinter::printOneOperand(const MachineOperand &mop,
 {
   bool needBitsFlag = true;
   
-  if (mop.opHiBits32())
+  if (mop.isHiBits32())
     toAsm << "%lm(";
-  else if (mop.opLoBits32())
+  else if (mop.isLoBits32())
     toAsm << "%lo(";
-  else if (mop.opHiBits64())
+  else if (mop.isHiBits64())
     toAsm << "%hh(";
-  else if (mop.opLoBits64())
+  else if (mop.isLoBits64())
     toAsm << "%hm(";
   else
     needBitsFlag = false;
diff --git a/lib/Target/SparcV9/SparcV9CodeEmitter.cpp b/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
index be677e0fdf..9a51faa4cc 100644
--- a/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
+++ b/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
@@ -699,13 +699,13 @@ int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI,
   // are used in SPARC assembly. (Some of these make no sense in combination
   // with some of the above; we'll trust that the instruction selector
   // will not produce nonsense, and not check for valid combinations here.)
-  if (MO.opLoBits32()) {          // %lo(val) == %lo() in Sparc ABI doc
+  if (MO.isLoBits32()) {          // %lo(val) == %lo() in Sparc ABI doc
     return rv & 0x03ff;
-  } else if (MO.opHiBits32()) {   // %lm(val) == %hi() in Sparc ABI doc
+  } else if (MO.isHiBits32()) {   // %lm(val) == %hi() in Sparc ABI doc
     return (rv >> 10) & 0x03fffff;
-  } else if (MO.opLoBits64()) {   // %hm(val) == %ulo() in Sparc ABI doc
+  } else if (MO.isLoBits64()) {   // %hm(val) == %ulo() in Sparc ABI doc
     return (rv >> 32) & 0x03ff;
-  } else if (MO.opHiBits64()) {   // %hh(val) == %uhi() in Sparc ABI doc
+  } else if (MO.isHiBits64()) {   // %hh(val) == %uhi() in Sparc ABI doc
     return rv >> 42;
   } else {                        // (unadorned) val
     return rv;
@@ -747,10 +747,10 @@ bool SparcV9CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
         int64_t branchTarget = (Location - (long)Ref) >> 2;
         // Save the flags.
         bool loBits32=false, hiBits32=false, loBits64=false, hiBits64=false;   
-        if (op.opLoBits32()) { loBits32=true; }
-        if (op.opHiBits32()) { hiBits32=true; }
-        if (op.opLoBits64()) { loBits64=true; }
-        if (op.opHiBits64()) { hiBits64=true; }
+        if (op.isLoBits32()) { loBits32=true; }
+        if (op.isHiBits32()) { hiBits32=true; }
+        if (op.isLoBits64()) { loBits64=true; }
+        if (op.isHiBits64()) { hiBits64=true; }
         MI->SetMachineOperandConst(ii, MachineOperand::MO_SignExtendedImmed,
                                    branchTarget);
         if (loBits32) { MI->setOperandLo32(ii); }
diff --git a/lib/Target/X86/PeepholeOptimizer.cpp b/lib/Target/X86/PeepholeOptimizer.cpp
index 4c887e1cff..89008aeeca 100644
--- a/lib/Target/X86/PeepholeOptimizer.cpp
+++ b/lib/Target/X86/PeepholeOptimizer.cpp
@@ -174,7 +174,7 @@ namespace {
           MachineInstr *MI = *I;
           for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
             MachineOperand &MO = MI->getOperand(i);
-            if (MO.isVirtualRegister() && MO.opIsDefOnly())
+            if (MO.isVirtualRegister() && MO.isDef() && !MO.isUse())
               setDefinition(MO.getReg(), MI);
           }
         }
@@ -233,7 +233,7 @@ namespace {
     /// register, return the machine instruction defining it, otherwise, return
     /// null.
     MachineInstr *getDefiningInst(MachineOperand &MO) {
-      if (!MO.opIsUse() || !MO.isVirtualRegister()) return 0;
+      if (MO.isDef() || !MO.isVirtualRegister()) return 0;
       return UDC->getDefinition(MO.getReg());
     }
 
diff --git a/lib/Target/X86/Printer.cpp b/lib/Target/X86/Printer.cpp
index 289a68b7f7..4d586c01f5 100644
--- a/lib/Target/X86/Printer.cpp
+++ b/lib/Target/X86/Printer.cpp
@@ -551,8 +551,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
       }
     } else {
       unsigned i = 0;
-      if (MI->getNumOperands() && (MI->getOperand(0).opIsDefOnly() || 
-                                   MI->getOperand(0).opIsDefAndUse())) {
+      if (MI->getNumOperands() && MI->getOperand(0).isDef()) {
 	printOp(MI->getOperand(0));
 	O << " = ";
 	++i;
@@ -561,11 +560,9 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
 
       for (unsigned e = MI->getNumOperands(); i != e; ++i) {
 	O << " ";
-	if (MI->getOperand(i).opIsDefOnly() || 
-            MI->getOperand(i).opIsDefAndUse()) O << "*";
+	if (MI->getOperand(i).isDef()) O << "*";
 	printOp(MI->getOperand(i));
-	if (MI->getOperand(i).opIsDefOnly() || 
-            MI->getOperand(i).opIsDefAndUse()) O << "*";
+	if (MI->getOperand(i).isDef()) O << "*";
       }
     }
     O << "\n";
diff --git a/lib/Target/X86/X86AsmPrinter.cpp b/lib/Target/X86/X86AsmPrinter.cpp
index 289a68b7f7..4d586c01f5 100644
--- a/lib/Target/X86/X86AsmPrinter.cpp
+++ b/lib/Target/X86/X86AsmPrinter.cpp
@@ -551,8 +551,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
       }
     } else {
       unsigned i = 0;
-      if (MI->getNumOperands() && (MI->getOperand(0).opIsDefOnly() || 
-                                   MI->getOperand(0).opIsDefAndUse())) {
+      if (MI->getNumOperands() && MI->getOperand(0).isDef()) {
 	printOp(MI->getOperand(0));
 	O << " = ";
 	++i;
@@ -561,11 +560,9 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
 
       for (unsigned e = MI->getNumOperands(); i != e; ++i) {
 	O << " ";
-	if (MI->getOperand(i).opIsDefOnly() || 
-            MI->getOperand(i).opIsDefAndUse()) O << "*";
+	if (MI->getOperand(i).isDef()) O << "*";
 	printOp(MI->getOperand(i));
-	if (MI->getOperand(i).opIsDefOnly() || 
-            MI->getOperand(i).opIsDefAndUse()) O << "*";
+	if (MI->getOperand(i).isDef()) O << "*";
       }
     }
     O << "\n";
diff --git a/lib/Target/X86/X86PeepholeOpt.cpp b/lib/Target/X86/X86PeepholeOpt.cpp
index 4c887e1cff..89008aeeca 100644
--- a/lib/Target/X86/X86PeepholeOpt.cpp
+++ b/lib/Target/X86/X86PeepholeOpt.cpp
@@ -174,7 +174,7 @@ namespace {
           MachineInstr *MI = *I;
           for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
             MachineOperand &MO = MI->getOperand(i);
-            if (MO.isVirtualRegister() && MO.opIsDefOnly())
+            if (MO.isVirtualRegister() && MO.isDef() && !MO.isUse())
               setDefinition(MO.getReg(), MI);
           }
         }
@@ -233,7 +233,7 @@ namespace {
     /// register, return the machine instruction defining it, otherwise, return
     /// null.
     MachineInstr *getDefiningInst(MachineOperand &MO) {
-      if (!MO.opIsUse() || !MO.isVirtualRegister()) return 0;
+      if (MO.isDef() || !MO.isVirtualRegister()) return 0;
       return UDC->getDefinition(MO.getReg());
     }