diff options
author | Devang Patel <dpatel@apple.com> | 2007-05-02 21:39:20 +0000 |
---|---|---|
committer | Devang Patel <dpatel@apple.com> | 2007-05-02 21:39:20 +0000 |
commit | 3e15bf33e024b9df9e89351a165acfdb1dde51ed (patch) | |
tree | 2a1b470e139345efc714c51846d285e5a52a9f12 /lib/Target | |
parent | 749a89bd53422c2aba0d78dc6e72a6d498b453e1 (diff) |
Use 'static const char' instead of 'static const int'.
Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36652 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/ARM/ARMConstantIslandPass.cpp | 4 | ||||
-rw-r--r-- | lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 4 | ||||
-rw-r--r-- | lib/Target/Alpha/AlphaBranchSelector.cpp | 4 | ||||
-rw-r--r-- | lib/Target/Alpha/AlphaCodeEmitter.cpp | 4 | ||||
-rw-r--r-- | lib/Target/Alpha/AlphaLLRP.cpp | 4 | ||||
-rw-r--r-- | lib/Target/CBackend/CBackend.cpp | 8 | ||||
-rw-r--r-- | lib/Target/IA64/IA64Bundling.cpp | 4 | ||||
-rw-r--r-- | lib/Target/MSIL/MSILWriter.cpp | 4 | ||||
-rw-r--r-- | lib/Target/MSIL/MSILWriter.h | 4 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCBranchSelector.cpp | 4 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCCodeEmitter.cpp | 4 | ||||
-rw-r--r-- | lib/Target/Sparc/DelaySlotFiller.cpp | 4 | ||||
-rw-r--r-- | lib/Target/Sparc/FPMover.cpp | 4 | ||||
-rw-r--r-- | lib/Target/TargetData.cpp | 2 | ||||
-rw-r--r-- | lib/Target/X86/X86CodeEmitter.cpp | 4 | ||||
-rw-r--r-- | lib/Target/X86/X86FloatingPoint.cpp | 4 |
16 files changed, 33 insertions, 33 deletions
diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp index 0850d22994..405ac0a2c6 100644 --- a/lib/Target/ARM/ARMConstantIslandPass.cpp +++ b/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -128,7 +128,7 @@ namespace { ARMFunctionInfo *AFI; bool isThumb; public: - static const int ID; + static const char ID; ARMConstantIslands() : MachineFunctionPass((intptr_t)&ID) {} virtual bool runOnMachineFunction(MachineFunction &Fn); @@ -174,7 +174,7 @@ namespace { void dumpBBs(); void verify(MachineFunction &Fn); }; - const int ARMConstantIslands::ID = 0; + const char ARMConstantIslands::ID = 0; } /// verify - check BBOffsets, BBSizes, alignment of islands diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 143fa1bbda..83509d8518 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -38,7 +38,7 @@ STATISTIC(NumFSTMGened, "Number of fstm instructions generated"); namespace { struct VISIBILITY_HIDDEN ARMLoadStoreOpt : public MachineFunctionPass { - static const int ID; + static const char ID; ARMLoadStoreOpt() : MachineFunctionPass((intptr_t)&ID) {} const TargetInstrInfo *TII; @@ -73,7 +73,7 @@ namespace { bool LoadStoreMultipleOpti(MachineBasicBlock &MBB); bool MergeReturnIntoLDM(MachineBasicBlock &MBB); }; - const int ARMLoadStoreOpt::ID = 0; + const char ARMLoadStoreOpt::ID = 0; } /// createARMLoadStoreOptimizationPass - returns an instance of the load / store diff --git a/lib/Target/Alpha/AlphaBranchSelector.cpp b/lib/Target/Alpha/AlphaBranchSelector.cpp index f0f70adffe..a9b9c63233 100644 --- a/lib/Target/Alpha/AlphaBranchSelector.cpp +++ b/lib/Target/Alpha/AlphaBranchSelector.cpp @@ -22,7 +22,7 @@ using namespace llvm; namespace { struct VISIBILITY_HIDDEN AlphaBSel : public MachineFunctionPass { - static const int ID; + static const char ID; AlphaBSel() : MachineFunctionPass((intptr_t)&ID) {} virtual bool runOnMachineFunction(MachineFunction &Fn); @@ -31,7 +31,7 @@ namespace { return "Alpha Branch Selection"; } }; - const int AlphaBSel::ID = 0; + const char AlphaBSel::ID = 0; } /// createAlphaBranchSelectionPass - returns an instance of the Branch Selection diff --git a/lib/Target/Alpha/AlphaCodeEmitter.cpp b/lib/Target/Alpha/AlphaCodeEmitter.cpp index 006e57176e..23552fa69a 100644 --- a/lib/Target/Alpha/AlphaCodeEmitter.cpp +++ b/lib/Target/Alpha/AlphaCodeEmitter.cpp @@ -36,7 +36,7 @@ namespace { int getMachineOpValue(MachineInstr &MI, MachineOperand &MO); public: - static const int ID; + static const char ID; explicit AlphaCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce) : MachineFunctionPass((intptr_t)&ID), II(0), TM(tm), MCE(mce) {} AlphaCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce, @@ -61,7 +61,7 @@ namespace { void emitBasicBlock(MachineBasicBlock &MBB); }; - const int AlphaCodeEmitter::ID = 0; + const char AlphaCodeEmitter::ID = 0; } /// createAlphaCodeEmitterPass - Return a pass that emits the collected Alpha code diff --git a/lib/Target/Alpha/AlphaLLRP.cpp b/lib/Target/Alpha/AlphaLLRP.cpp index c5a20e7a0c..ee745b52b3 100644 --- a/lib/Target/Alpha/AlphaLLRP.cpp +++ b/lib/Target/Alpha/AlphaLLRP.cpp @@ -37,7 +37,7 @@ namespace { /// AlphaTargetMachine &TM; - static const int ID; + static const char ID; AlphaLLRPPass(AlphaTargetMachine &tm) : MachineFunctionPass((intptr_t)&ID), TM(tm) { } @@ -154,7 +154,7 @@ namespace { return Changed; } }; - const int AlphaLLRPPass::ID = 0; + const char AlphaLLRPPass::ID = 0; } // end of anonymous namespace FunctionPass *llvm::createAlphaLLRPPass(AlphaTargetMachine &tm) { diff --git a/lib/Target/CBackend/CBackend.cpp b/lib/Target/CBackend/CBackend.cpp index cbf480e855..0fd03e003b 100644 --- a/lib/Target/CBackend/CBackend.cpp +++ b/lib/Target/CBackend/CBackend.cpp @@ -57,7 +57,7 @@ namespace { /// class CBackendNameAllUsedStructsAndMergeFunctions : public ModulePass { public: - static const int ID; + static const char ID; CBackendNameAllUsedStructsAndMergeFunctions() : ModulePass((intptr_t)&ID) {} void getAnalysisUsage(AnalysisUsage &AU) const { @@ -71,7 +71,7 @@ namespace { virtual bool runOnModule(Module &M); }; - const int CBackendNameAllUsedStructsAndMergeFunctions::ID = 0; + const char CBackendNameAllUsedStructsAndMergeFunctions::ID = 0; /// CWriter - This class is the main chunk of code that converts an LLVM /// module to a C translation unit. @@ -88,7 +88,7 @@ namespace { std::set<Function*> intrinsicPrototypesAlreadyGenerated; public: - static const int ID; + static const char ID; CWriter(std::ostream &o) : FunctionPass((intptr_t)&ID), Out(o), IL(0), Mang(0), LI(0), TheModule(0), TAsm(0), TD(0) {} @@ -264,7 +264,7 @@ namespace { }; } -const int CWriter::ID = 0; +const char CWriter::ID = 0; /// This method inserts names for any unnamed structure types that are used by /// the program, and removes names from structure types that are not used by the diff --git a/lib/Target/IA64/IA64Bundling.cpp b/lib/Target/IA64/IA64Bundling.cpp index 89732aed5f..afe029c286 100644 --- a/lib/Target/IA64/IA64Bundling.cpp +++ b/lib/Target/IA64/IA64Bundling.cpp @@ -36,7 +36,7 @@ STATISTIC(StopBitsAdded, "Number of stop bits added"); namespace { struct IA64BundlingPass : public MachineFunctionPass { - static const int ID; + static const char ID; /// Target machine description which we query for reg. names, data /// layout, etc. /// @@ -63,7 +63,7 @@ namespace { // 'fallthrough' code std::set<unsigned> PendingRegWrites; }; - const int IA64BundlingPass::ID = 0; + const char IA64BundlingPass::ID = 0; } // end of anonymous namespace /// createIA64BundlingPass - Returns a pass that adds STOP (;;) instructions diff --git a/lib/Target/MSIL/MSILWriter.cpp b/lib/Target/MSIL/MSILWriter.cpp index 86bea59db4..029094c418 100644 --- a/lib/Target/MSIL/MSILWriter.cpp +++ b/lib/Target/MSIL/MSILWriter.cpp @@ -80,8 +80,8 @@ bool MSILModule::runOnModule(Module &M) { return Changed; } -const int MSILModule::ID = 0; -const int MSILWriter::ID = 0; +const char MSILModule::ID = 0; +const char MSILWriter::ID = 0; bool MSILWriter::runOnFunction(Function &F) { if (F.isDeclaration()) return false; diff --git a/lib/Target/MSIL/MSILWriter.h b/lib/Target/MSIL/MSILWriter.h index 15a463d73d..6746d67a68 100644 --- a/lib/Target/MSIL/MSILWriter.h +++ b/lib/Target/MSIL/MSILWriter.h @@ -37,7 +37,7 @@ namespace { const TargetData*& TD; public: - static const int ID; + static const char ID; MSILModule(const std::set<const Type *>*& _UsedTypes, const TargetData*& _TD) : ModulePass((intptr_t)&ID), UsedTypes(_UsedTypes), TD(_TD) {} @@ -83,7 +83,7 @@ namespace { std::map<const GlobalVariable*,std::vector<StaticInitializer> > StaticInitList; const std::set<const Type *>* UsedTypes; - static const int ID; + static const char ID; MSILWriter(std::ostream &o) : FunctionPass((intptr_t)&ID), Out(o) { UniqID = 0; } diff --git a/lib/Target/PowerPC/PPCBranchSelector.cpp b/lib/Target/PowerPC/PPCBranchSelector.cpp index a4f0caee8a..28a61c09e8 100644 --- a/lib/Target/PowerPC/PPCBranchSelector.cpp +++ b/lib/Target/PowerPC/PPCBranchSelector.cpp @@ -32,7 +32,7 @@ STATISTIC(NumExpanded, "Number of branches expanded to long format"); namespace { struct VISIBILITY_HIDDEN PPCBSel : public MachineFunctionPass { - static const int ID; + static const char ID; PPCBSel() : MachineFunctionPass((intptr_t)&ID) {} /// BlockSizes - The sizes of the basic blocks in the function. @@ -44,7 +44,7 @@ namespace { return "PowerPC Branch Selector"; } }; - const int PPCBSel::ID = 0; + const char PPCBSel::ID = 0; } /// createPPCBranchSelectionPass - returns an instance of the Branch Selection diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp index acca7a30eb..cffc128089 100644 --- a/lib/Target/PowerPC/PPCCodeEmitter.cpp +++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp @@ -40,7 +40,7 @@ namespace { int getMachineOpValue(MachineInstr &MI, MachineOperand &MO); public: - static const int ID; + static const char ID; PPCCodeEmitter(TargetMachine &T, MachineCodeEmitter &M) : MachineFunctionPass((intptr_t)&ID), TM(T), MCE(M) {} @@ -64,7 +64,7 @@ namespace { /// unsigned getBinaryCodeForInstr(MachineInstr &MI); }; - const int PPCCodeEmitter::ID = 0; + const char PPCCodeEmitter::ID = 0; } /// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code diff --git a/lib/Target/Sparc/DelaySlotFiller.cpp b/lib/Target/Sparc/DelaySlotFiller.cpp index 313eab9319..57eb1a1c9c 100644 --- a/lib/Target/Sparc/DelaySlotFiller.cpp +++ b/lib/Target/Sparc/DelaySlotFiller.cpp @@ -30,7 +30,7 @@ namespace { TargetMachine &TM; const TargetInstrInfo *TII; - static const int ID; + static const char ID; Filler(TargetMachine &tm) : MachineFunctionPass((intptr_t)&ID), TM(tm), TII(tm.getInstrInfo()) { } @@ -48,7 +48,7 @@ namespace { } }; - const int Filler::ID = 0; + const char Filler::ID = 0; } // end of anonymous namespace /// createSparcDelaySlotFillerPass - Returns a pass that fills in delay diff --git a/lib/Target/Sparc/FPMover.cpp b/lib/Target/Sparc/FPMover.cpp index 5596586f0c..ca70a9ceb4 100644 --- a/lib/Target/Sparc/FPMover.cpp +++ b/lib/Target/Sparc/FPMover.cpp @@ -32,7 +32,7 @@ namespace { /// TargetMachine &TM; - static const int ID; + static const char ID; FPMover(TargetMachine &tm) : MachineFunctionPass((intptr_t)&ID), TM(tm) { } @@ -43,7 +43,7 @@ namespace { bool runOnMachineBasicBlock(MachineBasicBlock &MBB); bool runOnMachineFunction(MachineFunction &F); }; - const int FPMover::ID = 0; + const char FPMover::ID = 0; } // end of anonymous namespace /// createSparcFPMoverPass - Returns a pass that turns FpMOVD diff --git a/lib/Target/TargetData.cpp b/lib/Target/TargetData.cpp index 9492c8aad2..d4c9e58c47 100644 --- a/lib/Target/TargetData.cpp +++ b/lib/Target/TargetData.cpp @@ -35,7 +35,7 @@ namespace { // Register the default SparcV9 implementation... RegisterPass<TargetData> X("targetdata", "Target Data Layout"); } -const int TargetData::ID = 0; +const char TargetData::ID = 0; //===----------------------------------------------------------------------===// // Support for StructLayout diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index db80d9f892..244ddc0a9e 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -39,7 +39,7 @@ namespace { MachineCodeEmitter &MCE; bool Is64BitMode; public: - static const int ID; + static const char ID; explicit Emitter(TargetMachine &tm, MachineCodeEmitter &mce) : MachineFunctionPass((intptr_t)&ID), II(0), TD(0), TM(tm), MCE(mce), Is64BitMode(false) {} @@ -82,7 +82,7 @@ namespace { bool isX86_64ExtendedReg(const MachineOperand &MO); unsigned determineREX(const MachineInstr &MI); }; - const int Emitter::ID = 0; + const char Emitter::ID = 0; } /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp index 4667b91ba6..9a048ccb72 100644 --- a/lib/Target/X86/X86FloatingPoint.cpp +++ b/lib/Target/X86/X86FloatingPoint.cpp @@ -52,7 +52,7 @@ STATISTIC(NumFP , "Number of floating point instructions"); namespace { struct VISIBILITY_HIDDEN FPS : public MachineFunctionPass { - static const int ID; + static const char ID; FPS() : MachineFunctionPass((intptr_t)&ID) {} virtual bool runOnMachineFunction(MachineFunction &MF); @@ -154,7 +154,7 @@ namespace { void handleCondMovFP(MachineBasicBlock::iterator &I); void handleSpecialFP(MachineBasicBlock::iterator &I); }; - const int FPS::ID = 0; + const char FPS::ID = 0; } FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); } |