diff options
| author | Tom Stellard <thomas.stellard@amd.com> | 2013-01-23 21:39:49 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-01-23 21:39:49 +0000 |
| commit | 254a83e46c0ffb08c5c77d99f64d6e86db550c6f (patch) | |
| tree | 75726a515395085c36899f35521ae2d759dc7c0c /lib/Target | |
| parent | 2a3e0d7e76079289e2b007a15c311c51218f0b89 (diff) | |
R600: Add a llvm.R600.store.swizzle intrinsics
This intrinsic is translated to ALLOC_EXPORT_WORD1_SWIZ, hence its
name. It is used to store vs/fs outputs
Patch by: Vincent Lejeune
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173297 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/R600/R600ISelLowering.cpp | 20 | ||||
| -rw-r--r-- | lib/Target/R600/R600Instructions.td | 11 | ||||
| -rw-r--r-- | lib/Target/R600/R600Intrinsics.td | 2 |
3 files changed, 31 insertions, 2 deletions
diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp index 3434d7ec7d..3dc5b0076e 100644 --- a/lib/Target/R600/R600ISelLowering.cpp +++ b/lib/Target/R600/R600ISelLowering.cpp @@ -269,8 +269,24 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter( case AMDGPU::EG_ExportSwz: case AMDGPU::R600_ExportSwz: { + // Instruction is left unmodified if its not the last one of its type + bool isLastInstructionOfItsType = true; + unsigned InstExportType = MI->getOperand(1).getImm(); + for (MachineBasicBlock::iterator NextExportInst = llvm::next(I), + EndBlock = BB->end(); NextExportInst != EndBlock; + NextExportInst = llvm::next(NextExportInst)) { + if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz || + NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) { + unsigned CurrentInstExportType = NextExportInst->getOperand(1) + .getImm(); + if (CurrentInstExportType == InstExportType) { + isLastInstructionOfItsType = false; + break; + } + } + } bool EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN)? 1 : 0; - if (!EOP) + if (!EOP && !isLastInstructionOfItsType) return BB; unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40; BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode())) @@ -282,7 +298,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter( .addOperand(MI->getOperand(5)) .addOperand(MI->getOperand(6)) .addImm(CfInst) - .addImm(1); + .addImm(EOP); break; } } diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td index 3e069da780..04b83bc87b 100644 --- a/lib/Target/R600/R600Instructions.td +++ b/lib/Target/R600/R600Instructions.td @@ -599,6 +599,17 @@ multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> { (ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase, 0, 1, 2, 3, cf_inst, 0) >; + def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 1), + (i32 imm:$type), (i32 imm:$arraybase), (i32 imm)), + (ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase, + 0, 1, 2, 3, cf_inst, 0) + >; + + def : Pat<(int_R600_store_swizzle (v4f32 R600_Reg128:$src), imm:$arraybase, + imm:$type), + (ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase, + 0, 1, 2, 3, cf_inst, 0) + >; } multiclass SteamOutputExportPattern<Instruction ExportInst, diff --git a/lib/Target/R600/R600Intrinsics.td b/lib/Target/R600/R600Intrinsics.td index 06a734123f..1394a85461 100644 --- a/lib/Target/R600/R600Intrinsics.td +++ b/lib/Target/R600/R600Intrinsics.td @@ -19,6 +19,8 @@ let TargetPrefix = "R600", isTarget = 1 in { Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrReadMem]>; def int_R600_load_input_linear : Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrReadMem]>; + def int_R600_store_swizzle : + Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>; def int_R600_store_stream_output : Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; def int_R600_store_pixel_color : |