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authorMisha Brukman <brukman+llvm@gmail.com>2004-10-14 06:04:56 +0000
committerMisha Brukman <brukman+llvm@gmail.com>2004-10-14 06:04:56 +0000
commitbab2adf49691014fedcffe0744e22e0277ddf1b8 (patch)
tree033c52b1723358ff240e6b3175de7f228f35bdb2 /lib/Target
parenta6457507223e50345f59c3c58488186dd30a4f76 (diff)
* Make a PPC32-specific code emitter because we have separate classes for 32-
and 64-bit code emitters that cannot share code unless we use virtual functions * Identify components being built by tablegen with more detail by assigning them to PowerPC, PPC32, or PPC64 more specifically; also avoids seeing 'building PowerPC XYZ' messages twice, where one is for PPC32 and one for PPC64 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16980 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r--lib/Target/PowerPC/Makefile12
1 files changed, 6 insertions, 6 deletions
diff --git a/lib/Target/PowerPC/Makefile b/lib/Target/PowerPC/Makefile
index d9cac3c2f8..e76bc3b286 100644
--- a/lib/Target/PowerPC/Makefile
+++ b/lib/Target/PowerPC/Makefile
@@ -14,14 +14,14 @@ TARGET = PowerPC
# Make sure that tblgen is run, first thing.
$(SourceDepend): PowerPCGenInstrNames.inc PowerPCGenRegisterNames.inc \
- PowerPCGenCodeEmitter.inc PowerPCGenAsmWriter.inc \
+ PowerPCGenAsmWriter.inc PPC32GenCodeEmitter.inc \
PPC32GenRegisterInfo.h.inc PPC32GenRegisterInfo.inc PPC32GenInstrInfo.inc \
PPC64GenRegisterInfo.h.inc PPC64GenRegisterInfo.inc PPC64GenInstrInfo.inc
TDFILES = $(wildcard $(SourceDir)/*.td) $(SourceDir)/../Target.td
%GenRegisterNames.inc:: PPC32.td $(TDFILES) $(TBLGEN)
- @echo "Building PowerPC register names with tblgen"
+ @echo "Building $(TARGET) register names with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
%GenRegisterInfo.h.inc:: %.td $(TDFILES) $(TBLGEN)
@@ -37,14 +37,14 @@ $(TARGET)GenInstrNames.inc:: PPC32.td $(TDFILES) $(TBLGEN)
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
%GenInstrInfo.inc:: %.td $(TDFILES) $(TBLGEN)
- @echo "Building $(TARGET) instruction information with tblgen"
+ @echo "Building `basename $<` instruction information with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
-$(TARGET)GenCodeEmitter.inc:: PPC32.td $(TDFILES) $(TBLGEN)
- @echo "Building $(TARGET) code emitter"
+%GenCodeEmitter.inc:: %.td $(TDFILES) $(TBLGEN)
+ @echo "Building `basename $<` code emitter with tblgen"
$(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-emitter -o $@
-$(TARGET)GenAsmWriter.inc:: PowerPC.td $(TDFILES) $(TBLGEN)
+$(TARGET)GenAsmWriter.inc:: $(TARGET).td $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td assembly writer with tblgen"
$(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-asm-writer -o $@