diff options
author | Chris Lattner <sabre@nondot.org> | 2008-01-06 23:38:27 +0000 |
---|---|---|
committer | Chris Lattner <sabre@nondot.org> | 2008-01-06 23:38:27 +0000 |
commit | 834f1ce0312e3d00d836f9560cb63182c2c4570f (patch) | |
tree | fa9d9d5b1ad73454fca5dd87fe5dd8b848b8bdc7 /lib/Target | |
parent | 9e7aba2739fb3edb3ddcf04c5d36c7c1cccb0581 (diff) |
rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/ARM/ARMInstrInfo.cpp | 2 | ||||
-rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 10 | ||||
-rw-r--r-- | lib/Target/ARM/ARMInstrThumb.td | 8 | ||||
-rw-r--r-- | lib/Target/ARM/ARMInstrVFP.td | 8 | ||||
-rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.cpp | 4 | ||||
-rw-r--r-- | lib/Target/Alpha/AlphaInstrFormats.td | 2 | ||||
-rw-r--r-- | lib/Target/Alpha/AlphaInstrInfo.td | 2 | ||||
-rw-r--r-- | lib/Target/CellSPU/SPUInstrInfo.td | 2 | ||||
-rw-r--r-- | lib/Target/IA64/IA64InstrInfo.td | 2 | ||||
-rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 2 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCHazardRecognizers.cpp | 2 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCInstr64Bit.td | 6 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCInstrAltivec.td | 2 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 4 | ||||
-rw-r--r-- | lib/Target/Target.td | 2 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrFPStack.td | 2 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 4 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrMMX.td | 4 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 24 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrX86-64.td | 2 |
20 files changed, 47 insertions, 47 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index b608d5f81e..aa0109f8b9 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -202,7 +202,7 @@ ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); const TargetInstrDescriptor *TID = MI->getInstrDescriptor(); unsigned NumOps = TID->numOperands; - bool isLoad = (TID->Flags & M_LOAD_FLAG) != 0; + bool isLoad = TID->isSimpleLoad(); const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); const MachineOperand &Base = MI->getOperand(2); const MachineOperand &Offset = MI->getOperand(NumOps-3); diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index da294feb52..6b61d86b96 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -684,7 +684,7 @@ def PICADD : AXI1<0x0, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), Pseudo, "$cp:\n\tadd$p $dst, pc, $a", [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>; -let isLoad = 1, AddedComplexity = 10 in { +let isSimpleLoad = 1, AddedComplexity = 10 in { def PICLD : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), Pseudo, "${addr:label}:\n\tldr$p $dst, $addr", [(set GPR:$dst, (load addrmodepc:$addr))]>; @@ -738,7 +738,7 @@ let isReturn = 1, isTerminator = 1 in // FIXME: remove when we have a way to marking a MI with these properties. // FIXME: $dst1 should be a def. But the extra ops must be in the end of the // operand list. -let isLoad = 1, isReturn = 1, isTerminator = 1 in +let isSimpleLoad = 1, isReturn = 1, isTerminator = 1 in def LDM_RET : AXI4<0x0, (outs), (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), LdFrm, "ldm${p}${addr:submode} $addr, $dst1", @@ -802,7 +802,7 @@ let isBranch = 1, isTerminator = 1 in { // // Load -let isLoad = 1 in { +let isSimpleLoad = 1 in { def LDR : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm, "ldr", " $dst, $addr", [(set GPR:$dst, (load addrmode2:$addr))]>; @@ -875,7 +875,7 @@ def LDRSB_PRE : AI3pr<0xD, (outs GPR:$dst, GPR:$base_wb), def LDRSB_POST: AI3po<0xD, (outs GPR:$dst, GPR:$base_wb), (ins GPR:$base,am3offset:$offset), LdFrm, "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>; -} // isLoad +} // isSimpleLoad // Store def STR : AI2<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm, @@ -939,7 +939,7 @@ def STRB_POST: AI2po<0x1, (outs GPR:$base_wb), // // FIXME: $dst1 should be a def. -let isLoad = 1 in +let isSimpleLoad = 1 in def LDM : AXI4<0x0, (outs), (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), LdFrm, "ldm${p}${addr:submode} $addr, $dst1", diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 2782f7d303..c8ed735b64 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -188,7 +188,7 @@ let isReturn = 1, isTerminator = 1 in { } // FIXME: remove when we have a way to marking a MI with these properties. -let isLoad = 1, isReturn = 1, isTerminator = 1 in +let isSimpleLoad = 1, isReturn = 1, isTerminator = 1 in def tPOP_RET : TI<(outs reglist:$dst1, variable_ops), (ins), "pop $dst1", []>; @@ -237,7 +237,7 @@ let isBranch = 1, isTerminator = 1 in // Load Store Instructions. // -let isLoad = 1 in { +let isSimpleLoad = 1 in { def tLDR : TI4<(outs GPR:$dst), (ins t_addrmode_s4:$addr), "ldr $dst, $addr", [(set GPR:$dst, (load t_addrmode_s4:$addr))]>; @@ -276,7 +276,7 @@ def tLDRpci : TIs<(outs GPR:$dst), (ins i32imm:$addr), let isReMaterializable = 1 in def tLDRcp : TIs<(outs GPR:$dst), (ins i32imm:$addr), "ldr $dst, $addr", []>; -} // isLoad +} // isSimpleLoad def tSTR : TI4<(outs), (ins GPR:$src, t_addrmode_s4:$addr), "str $src, $addr", @@ -307,7 +307,7 @@ def tSpill : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr), // TODO: A7-44: LDMIA - load multiple -let isLoad = 1 in +let isSimpleLoad = 1 in def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins), "pop $dst1", []>; diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td index 89523f7b49..17c6a425ec 100644 --- a/lib/Target/ARM/ARMInstrVFP.td +++ b/lib/Target/ARM/ARMInstrVFP.td @@ -88,7 +88,7 @@ def arm_fmdrr : SDNode<"ARMISD::FMDRR", SDT_FMDRR>; // Load / store Instructions. // -let isLoad = 1 in { +let isSimpleLoad = 1 in { def FLDD : ADI5<(outs DPR:$dst), (ins addrmode5:$addr), "fldd", " $dst, $addr", [(set DPR:$dst, (load addrmode5:$addr))]>; @@ -96,7 +96,7 @@ def FLDD : ADI5<(outs DPR:$dst), (ins addrmode5:$addr), def FLDS : ASI5<(outs SPR:$dst), (ins addrmode5:$addr), "flds", " $dst, $addr", [(set SPR:$dst, (load addrmode5:$addr))]>; -} // isLoad +} // isSimpleLoad def FSTD : ADI5<(outs), (ins DPR:$src, addrmode5:$addr), "fstd", " $src, $addr", @@ -110,7 +110,7 @@ def FSTS : ASI5<(outs), (ins SPR:$src, addrmode5:$addr), // Load / store multiple Instructions. // -let isLoad = 1 in { +let isSimpleLoad = 1 in { def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1, variable_ops), "fldm${addr:submode}d${p} ${addr:base}, $dst1", @@ -120,7 +120,7 @@ def FLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1, variable_ops), "fldm${addr:submode}s${p} ${addr:base}, $dst1", []>; -} // isLoad +} // isSimpleLoad let mayStore = 1 in { def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1, diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index ea775f74a1..316026234e 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -690,7 +690,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, } unsigned Opcode = MI.getOpcode(); - const TargetInstrDescriptor &Desc = TII.get(Opcode); + const TargetInstrDescriptor &Desc = *MI.getInstrDescriptor(); unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); bool isSub = false; @@ -885,7 +885,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, assert(Offset && "This code isn't needed if offset already handled!"); if (isThumb) { - if (TII.isLoad(Opcode)) { + if (Desc.isSimpleLoad()) { // Use the destination register to materialize sp + offset. unsigned TmpReg = MI.getOperand(0).getReg(); bool UseRR = false; diff --git a/lib/Target/Alpha/AlphaInstrFormats.td b/lib/Target/Alpha/AlphaInstrFormats.td index 2df4ebc1bb..366aea830a 100644 --- a/lib/Target/Alpha/AlphaInstrFormats.td +++ b/lib/Target/Alpha/AlphaInstrFormats.td @@ -41,7 +41,7 @@ class InstAlpha<bits<6> op, string asmstr, InstrItinClass itin> : Instruction { class MForm<bits<6> opcode, bit load, string asmstr, list<dag> pattern, InstrItinClass itin> : InstAlpha<opcode, asmstr, itin> { let Pattern = pattern; - let isLoad = load; + let isSimpleLoad = load; let Defs = [R28]; //We may use this for frame index calculations, so reserve it here bits<5> Ra; diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td index a8fec8adbc..db39644b6e 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.td +++ b/lib/Target/Alpha/AlphaInstrInfo.td @@ -152,7 +152,7 @@ def IDEF_F64 : PseudoInstAlpha<(outs F8RC:$RA), (ins), ";#idef $RA", def WTF : PseudoInstAlpha<(outs), (ins variable_ops), "#wtf", [], s_pseudo>; -let isLoad = 1, hasCtrlDep = 1, Defs = [R30], Uses = [R30] in { +let hasCtrlDep = 1, Defs = [R30], Uses = [R30] in { def ADJUSTSTACKUP : PseudoInstAlpha<(outs), (ins s64imm:$amt), "; ADJUP $amt", [(callseq_start imm:$amt)], s_pseudo>; diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td index 8b9ed31dfb..2a0eef7f09 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.td +++ b/lib/Target/CellSPU/SPUInstrInfo.td @@ -47,7 +47,7 @@ def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$fi // finally the X-form with the register-register. //===----------------------------------------------------------------------===// -let isLoad = 1 in { +let isSimpleLoad = 1 in { def LQDv16i8: RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src), "lqd\t$rT, $src", LoadStore, diff --git a/lib/Target/IA64/IA64InstrInfo.td b/lib/Target/IA64/IA64InstrInfo.td index f308228933..5ab898b20e 100644 --- a/lib/Target/IA64/IA64InstrInfo.td +++ b/lib/Target/IA64/IA64InstrInfo.td @@ -558,7 +558,7 @@ let mayStore = 1 in { "stf.spill [$dstPtr] = $value">, isM; } -let isLoad = 1 in { +let isSimpleLoad = 1 in { def LD1 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$srcPtr), "ld1 $dst = [$srcPtr]">, isM; def LD2 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$srcPtr), diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index bc5e7f566d..43313e2106 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -205,7 +205,7 @@ class LoadUpper<bits<6> op, string instr_asm>: [], IIAlu>; // Memory Load/Store -let isLoad = 1, hasDelaySlot = 1 in +let isSimpleLoad = 1, hasDelaySlot = 1 in class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>: FI< op, (outs CPURegs:$dst), diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/lib/Target/PowerPC/PPCHazardRecognizers.cpp index 03570aaeef..f081d149df 100644 --- a/lib/Target/PowerPC/PPCHazardRecognizers.cpp +++ b/lib/Target/PowerPC/PPCHazardRecognizers.cpp @@ -72,7 +72,7 @@ PPCHazardRecognizer970::GetInstrType(unsigned Opcode, const TargetInstrDescriptor &TID = TII.get(Opcode); - isLoad = TID.Flags & M_LOAD_FLAG; + isLoad = TID.isSimpleLoad(); isStore = TID.Flags & M_MAY_STORE_FLAG; unsigned TSFlags = TID.TSFlags; diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index 80167834a0..4e6348d399 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -365,7 +365,7 @@ def RLDICR : MDForm_1<30, 1, // Sign extending loads. -let isLoad = 1, PPC970_Unit = 2 in { +let isSimpleLoad = 1, PPC970_Unit = 2 in { def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src), "lha $rD, $src", LdStLHA, [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>, @@ -394,7 +394,7 @@ def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp, } // Zero extending loads. -let isLoad = 1, PPC970_Unit = 2 in { +let isSimpleLoad = 1, PPC970_Unit = 2 in { def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src), "lbz $rD, $src", LdStGeneral, [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>; @@ -433,7 +433,7 @@ def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), // Full 8-byte loads. -let isLoad = 1, PPC970_Unit = 2 in { +let isSimpleLoad = 1, PPC970_Unit = 2 in { def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src), "ld $rD, $src", LdStLD, [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64; diff --git a/lib/Target/PowerPC/PPCInstrAltivec.td b/lib/Target/PowerPC/PPCInstrAltivec.td index 7aaf035ba9..c006ce0bec 100644 --- a/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/lib/Target/PowerPC/PPCInstrAltivec.td @@ -202,7 +202,7 @@ def MTVSCR : VXForm_5<1604, (outs), (ins VRRC:$vB), "mtvscr $vB", LdStGeneral, [(int_ppc_altivec_mtvscr VRRC:$vB)]>; -let isLoad = 1, PPC970_Unit = 2 in { // Loads. +let isSimpleLoad = 1, PPC970_Unit = 2 in { // Loads. def LVEBX: XForm_1<31, 7, (outs VRRC:$vD), (ins memrr:$src), "lvebx $vD, $src", LdStGeneral, [(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>; diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index dc1ba09471..7b69d283b8 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -474,7 +474,7 @@ def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), // // Unindexed (r+i) Loads. -let isLoad = 1, PPC970_Unit = 2 in { +let isSimpleLoad = 1, PPC970_Unit = 2 in { def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src), "lbz $rD, $src", LdStGeneral, [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>; @@ -531,7 +531,7 @@ def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), // Indexed (r+r) Loads. // -let isLoad = 1, PPC970_Unit = 2 in { +let isSimpleLoad = 1, PPC970_Unit = 2 in { def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src), "lbzx $rD, $src", LdStGeneral, [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>; diff --git a/lib/Target/Target.td b/lib/Target/Target.td index 2e12070524..b64f65ea40 100644 --- a/lib/Target/Target.td +++ b/lib/Target/Target.td @@ -190,7 +190,7 @@ class Instruction { bit isIndirectBranch = 0; // Is this instruction an indirect branch? bit isBarrier = 0; // Can control flow fall through this instruction? bit isCall = 0; // Is this instruction a call instruction? - bit isLoad = 0; // Is this instruction a load instruction? + bit isSimpleLoad = 0; // Is this just a load instruction? bit mayStore = 0; // Can this instruction modify memory? bit isImplicitDef = 0; // Is this instruction an implicit def instruction? bit isTwoAddress = 0; // Is this a two address instruction? diff --git a/lib/Target/X86/X86InstrFPStack.td b/lib/Target/X86/X86InstrFPStack.td index 3784f3cd03..52f14093c0 100644 --- a/lib/Target/X86/X86InstrFPStack.td +++ b/lib/Target/X86/X86InstrFPStack.td @@ -346,7 +346,7 @@ def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins), "fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB; // Floating point loads & stores. -let isLoad = 1 in { +let isSimpleLoad = 1 in { def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP, [(set RFP32:$dst, (loadf32 addr:$src))]>; let isReMaterializable = 1, mayHaveSideEffects = 1 in diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 5f641076f0..37119862bf 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -586,7 +586,7 @@ def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), "mov{l}\t{$src, $dst|$dst, $src}", [(store (i32 imm:$src), addr:$dst)]>; -let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in { +let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in { def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), "mov{b}\t{$src, $dst|$dst, $src}", [(set GR8:$dst, (load addr:$src))]>; @@ -2488,7 +2488,7 @@ def MOV16_rr : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16_:$src), "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize; def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src), "mov{l}\t{$src, $dst|$dst, $src}", []>; -let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in { +let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in { def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src), "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize; def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src), diff --git a/lib/Target/X86/X86InstrMMX.td b/lib/Target/X86/X86InstrMMX.td index 0589bf1fe6..96b50e05f9 100644 --- a/lib/Target/X86/X86InstrMMX.td +++ b/lib/Target/X86/X86InstrMMX.td @@ -158,7 +158,7 @@ def MMX_FEMMS : MMXI<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)] // Data Transfer Instructions def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src), "movd\t{$src, $dst|$dst, $src}", []>; -let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in +let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src), "movd\t{$src, $dst|$dst, $src}", []>; def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src), @@ -169,7 +169,7 @@ def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src), def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src), "movq\t{$src, $dst|$dst, $src}", []>; -let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in +let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src), "movq\t{$src, $dst|$dst, $src}", [(set VR64:$dst, (load_mmx addr:$src))]>; diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 65ac99ce65..3c2eb6f41b 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -301,7 +301,7 @@ let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in { // Move Instructions def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src), "movss\t{$src, $dst|$dst, $src}", []>; -let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in +let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src), "movss\t{$src, $dst|$dst, $src}", [(set FR32:$dst, (loadf32 addr:$src))]>; @@ -457,7 +457,7 @@ def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src), // Alias instruction to load FR32 from f128mem using movaps. Upper bits are // disregarded. -let isLoad = 1 in +let isSimpleLoad = 1 in def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src), "movaps\t{$src, $dst|$dst, $src}", [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>; @@ -634,7 +634,7 @@ defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin, // Move Instructions def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "movaps\t{$src, $dst|$dst, $src}", []>; -let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in +let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "movaps\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>; @@ -645,7 +645,7 @@ def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "movups\t{$src, $dst|$dst, $src}", []>; -let isLoad = 1 in +let isSimpleLoad = 1 in def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "movups\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (loadv4f32 addr:$src))]>; @@ -654,7 +654,7 @@ def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), [(store (v4f32 VR128:$src), addr:$dst)]>; // Intrinsic forms of MOVUPS load and store -let isLoad = 1 in +let isSimpleLoad = 1 in def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "movups\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>; @@ -1003,7 +1003,7 @@ def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src), // Move Instructions def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src), "movsd\t{$src, $dst|$dst, $src}", []>; -let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in +let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src), "movsd\t{$src, $dst|$dst, $src}", [(set FR64:$dst, (loadf64 addr:$src))]>; @@ -1153,7 +1153,7 @@ def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src), // Alias instruction to load FR64 from f128mem using movapd. Upper bits are // disregarded. -let isLoad = 1 in +let isSimpleLoad = 1 in def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src), "movapd\t{$src, $dst|$dst, $src}", [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>; @@ -1330,7 +1330,7 @@ defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin, // Move Instructions def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "movapd\t{$src, $dst|$dst, $src}", []>; -let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in +let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "movapd\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>; @@ -1341,7 +1341,7 @@ def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "movupd\t{$src, $dst|$dst, $src}", []>; -let isLoad = 1 in +let isSimpleLoad = 1 in def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "movupd\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (loadv2f64 addr:$src))]>; @@ -1704,14 +1704,14 @@ let isTwoAddress = 1 in { // Move Instructions def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "movdqa\t{$src, $dst|$dst, $src}", []>; -let isLoad = 1 in +let isSimpleLoad = 1 in def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), "movdqa\t{$src, $dst|$dst, $src}", [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>; def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src), "movdqa\t{$src, $dst|$dst, $src}", [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>; -let isLoad = 1 in +let isSimpleLoad = 1 in def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), "movdqu\t{$src, $dst|$dst, $src}", [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>, @@ -1722,7 +1722,7 @@ def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src), XS, Requires<[HasSSE2]>; // Intrinsic forms of MOVDQU load and store -let isLoad = 1 in +let isSimpleLoad = 1 in def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), "movdqu\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>, diff --git a/lib/Target/X86/X86InstrX86-64.td b/lib/Target/X86/X86InstrX86-64.td index af8957f006..bfdb45750e 100644 --- a/lib/Target/X86/X86InstrX86-64.td +++ b/lib/Target/X86/X86InstrX86-64.td @@ -210,7 +210,7 @@ def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src), [(set GR64:$dst, i64immSExt32:$src)]>; } -let isLoad = 1 in +let isSimpleLoad = 1 in def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), "mov{q}\t{$src, $dst|$dst, $src}", [(set GR64:$dst, (load addr:$src))]>; |