Implement Value* tracking for loads and stores in the selection DAG. This enables one to use alias analysis in the backends.

(TRUNK)Stores and (EXT|ZEXT|SEXT)Loads have an extra SDOperand which is a SrcValueSDNode which contains the Value*.  Note that if the operation is introduced by the backend, it will still have the operand, but the value* will be null.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21599 91177308-0d34-0410-b5e6-96231b3b80d8

5 files changed, 28 insertions, 28 deletions

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 450de9f491..e2e863deac 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -229,7 +229,7 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
       //from this parameter
       SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
       argt = newroot = DAG.getLoad(getValueType(I->getType()),
-                                   DAG.getEntryNode(), FIN);
+                                   DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
     }
     ++count;
     LS.push_back(newroot.getValue(1));
@@ -245,14 +245,14 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
       SDOperand argt = DAG.getCopyFromReg(Vreg, MVT::i64, Chain);
       int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
       SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
-      LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, argt, SDFI));
+      LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, argt, SDFI, DAG.getSrcValue(NULL)));
 
       Vreg = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::f64));
       BuildMI(&BB, Alpha::CPYS, 2, Vreg).addReg(args_float[i]).addReg(args_float[i]);
       argt = DAG.getCopyFromReg(Vreg, MVT::f64, Chain);
       FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
       SDFI = DAG.getFrameIndex(FI, MVT::i64);
-      LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, argt, SDFI));
+      LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, argt, SDFI, DAG.getSrcValue(NULL)));
     }
 
   // If the function takes variable number of arguments, make a frame index for
diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp
index 8580febe9b..c3675a0da0 100644
--- a/lib/Target/IA64/IA64ISelPattern.cpp
+++ b/lib/Target/IA64/IA64ISelPattern.cpp
@@ -223,7 +223,7 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
         //from this parameter
         SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
         argt = newroot = DAG.getLoad(getValueType(I->getType()),
-            DAG.getEntryNode(), FIN);
+                                     DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
       }
       ++count;
       DAG.setRoot(newroot.getValue(1));
@@ -378,7 +378,7 @@ LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
   MVT::ValueType ArgVT = getValueType(ArgTy);
   SDOperand Result;
   if (!isVANext) {
-    Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList);
+    Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList, DAG.getSrcValue(NULL));
   } else {
     unsigned Amt;
     if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
diff --git a/lib/Target/PowerPC/PPC64ISelPattern.cpp b/lib/Target/PowerPC/PPC64ISelPattern.cpp
index e5c2f40e3c..1e72bf0ba6 100644
--- a/lib/Target/PowerPC/PPC64ISelPattern.cpp
+++ b/lib/Target/PowerPC/PPC64ISelPattern.cpp
@@ -176,7 +176,7 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
       SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
       FIN = DAG.getNode(ISD::ADD, MVT::i64, FIN,
                         DAG.getConstant(SubregOffset, MVT::i64));
-      argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
+      argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
     }
 
     // Every 4 bytes of argument space consumes one of the GPRs available for
@@ -204,7 +204,7 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
       BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
       SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i64, DAG.getRoot());
       SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
-                                    Val, FIN);
+                                    Val, FIN, DAG.getSrcValue(NULL));
       MemOps.push_back(Store);
       // Increment the address by eight for the next argument to store
       SDOperand PtrOff = DAG.getConstant(8, getPointerTy());
@@ -285,7 +285,7 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain,
           --GPR_remaining;
         } else {
           MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                          Args[i].first, PtrOff));
+                                          Args[i].first, PtrOff, DAG.getSrcValue(NULL)));
         }
         ArgOffset += 8;
         break;
@@ -296,11 +296,11 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain,
           --FPR_remaining;
           if (isVarArg) {
             SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                          Args[i].first, PtrOff);
+                                          Args[i].first, PtrOff, DAG.getSrcValue(NULL));
             MemOps.push_back(Store);
             // Float varargs are always shadowed in available integer registers
             if (GPR_remaining > 0) {
-              SDOperand Load = DAG.getLoad(MVT::i64, Store, PtrOff);
+              SDOperand Load = DAG.getLoad(MVT::i64, Store, PtrOff, DAG.getSrcValue(NULL));
               MemOps.push_back(Load);
               args_to_use.push_back(Load);
               --GPR_remaining;
@@ -315,7 +315,7 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain,
           }
         } else {
           MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                          Args[i].first, PtrOff));
+                                          Args[i].first, PtrOff, DAG.getSrcValue(NULL)));
         }
         ArgOffset += 8;
         break;
@@ -351,7 +351,7 @@ LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
   MVT::ValueType ArgVT = getValueType(ArgTy);
   SDOperand Result;
   if (!isVANext) {
-    Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList);
+    Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList, DAG.getSrcValue(NULL));
   } else {
     Result = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
                          DAG.getConstant(8, VAList.getValueType()));
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index a516a8b3c8..40a2610f2c 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -164,7 +164,7 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
         } else {
           int FI = MFI->CreateFixedObject(4, ArgOffset+4);
           SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
-          argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN);
+          argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
         }
         // Build the outgoing arg thingy
         argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
@@ -199,7 +199,7 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
       SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
       FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
                         DAG.getConstant(SubregOffset, MVT::i32));
-      argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
+      argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
     }
 
     // Every 4 bytes of argument space consumes one of the GPRs available for
@@ -229,7 +229,7 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
       MF.addLiveIn(GPR[GPR_idx]);
       SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
       SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
-                                    Val, FIN);
+                                    Val, FIN, DAG.getSrcValue(NULL));
       MemOps.push_back(Store);
       // Increment the address by four for the next argument to store
       SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
@@ -343,7 +343,7 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
           --GPR_remaining;
         } else {
           MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                          Args[i].first, PtrOff));
+                                       Args[i].first, PtrOff, DAG.getSrcValue(NULL)));
         }
         ArgOffset += 4;
         break;
@@ -365,11 +365,11 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
             SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
             PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
             MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                            Lo, PtrOff));
+                                         Lo, PtrOff, DAG.getSrcValue(NULL)));
           }
         } else {
           MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                          Args[i].first, PtrOff));
+                                       Args[i].first, PtrOff, DAG.getSrcValue(NULL)));
         }
         ArgOffset += 8;
         break;
@@ -380,11 +380,11 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
           --FPR_remaining;
           if (isVarArg) {
             SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                          Args[i].first, PtrOff);
+                                          Args[i].first, PtrOff, DAG.getSrcValue(NULL));
             MemOps.push_back(Store);
             // Float varargs are always shadowed in available integer registers
             if (GPR_remaining > 0) {
-              SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff);
+              SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, DAG.getSrcValue(NULL));
               MemOps.push_back(Load);
               args_to_use.push_back(Load);
               --GPR_remaining;
@@ -392,7 +392,7 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
             if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
               SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
               PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
-              SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff);
+              SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, DAG.getSrcValue(NULL));
               MemOps.push_back(Load);
               args_to_use.push_back(Load);
               --GPR_remaining;
@@ -412,7 +412,7 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
           }
         } else {
           MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                          Args[i].first, PtrOff));
+                                       Args[i].first, PtrOff, DAG.getSrcValue(NULL)));
         }
         ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
         break;
@@ -448,7 +448,7 @@ LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
   MVT::ValueType ArgVT = getValueType(ArgTy);
   SDOperand Result;
   if (!isVANext) {
-    Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList);
+    Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList, DAG.getSrcValue(NULL));
   } else {
     unsigned Amt;
     if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp
index e92ef0ab35..bb9e901e1e 100644
--- a/lib/Target/X86/X86ISelPattern.cpp
+++ b/lib/Target/X86/X86ISelPattern.cpp
@@ -141,7 +141,7 @@ X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
     // dead loads.
     SDOperand ArgValue;
     if (!I->use_empty())
-      ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
+      ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
     else {
       if (MVT::isInteger(ObjectVT))
         ArgValue = DAG.getConstant(0, ObjectVT);
@@ -239,13 +239,13 @@ X86TargetLowering::LowerCallTo(SDOperand Chain,
       case MVT::i32:
       case MVT::f32:
         Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                     Args[i].first, PtrOff));
+                                     Args[i].first, PtrOff, DAG.getSrcValue(NULL)));
         ArgOffset += 4;
         break;
       case MVT::i64:
       case MVT::f64:
         Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                     Args[i].first, PtrOff));
+                                     Args[i].first, PtrOff, DAG.getSrcValue(NULL)));
         ArgOffset += 8;
         break;
       }
@@ -278,7 +278,7 @@ LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
   MVT::ValueType ArgVT = getValueType(ArgTy);
   SDOperand Result;
   if (!isVANext) {
-    Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList);
+    Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList, DAG.getSrcValue(NULL));
   } else {
     unsigned Amt;
     if (ArgVT == MVT::i32)
@@ -312,7 +312,7 @@ LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
 
     if (!isFrameAddress)
       // Just load the return address
-      Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI);
+      Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI, DAG.getSrcValue(NULL));
     else
       Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI,
                            DAG.getConstant(4, MVT::i32));