Rename SDOperand to SDValue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8

34 files changed, 2542 insertions, 2542 deletions

diff --git a/lib/Target/ARM/ARMAddressingModes.h b/lib/Target/ARM/ARMAddressingModes.h
index 0189c00cea..2378485cd4 100644
--- a/lib/Target/ARM/ARMAddressingModes.h
+++ b/lib/Target/ARM/ARMAddressingModes.h
@@ -46,7 +46,7 @@ namespace ARM_AM {
     }
   }
   
-  static inline ShiftOpc getShiftOpcForNode(SDOperand N) {
+  static inline ShiftOpc getShiftOpcForNode(SDValue N) {
     switch (N.getOpcode()) {
     default:          return ARM_AM::no_shift;
     case ISD::SHL:    return ARM_AM::lsl;
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 2d1136f436..b79fffe16f 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -53,38 +53,38 @@ public:
     return "ARM Instruction Selection";
   } 
   
-  SDNode *Select(SDOperand Op);
+  SDNode *Select(SDValue Op);
   virtual void InstructionSelect(SelectionDAG &DAG);
-  bool SelectAddrMode2(SDOperand Op, SDOperand N, SDOperand &Base,
-                       SDOperand &Offset, SDOperand &Opc);
-  bool SelectAddrMode2Offset(SDOperand Op, SDOperand N,
-                             SDOperand &Offset, SDOperand &Opc);
-  bool SelectAddrMode3(SDOperand Op, SDOperand N, SDOperand &Base,
-                       SDOperand &Offset, SDOperand &Opc);
-  bool SelectAddrMode3Offset(SDOperand Op, SDOperand N,
-                             SDOperand &Offset, SDOperand &Opc);
-  bool SelectAddrMode5(SDOperand Op, SDOperand N, SDOperand &Base,
-                       SDOperand &Offset);
-
-  bool SelectAddrModePC(SDOperand Op, SDOperand N, SDOperand &Offset,
-                         SDOperand &Label);
-
-  bool SelectThumbAddrModeRR(SDOperand Op, SDOperand N, SDOperand &Base,
-                             SDOperand &Offset);
-  bool SelectThumbAddrModeRI5(SDOperand Op, SDOperand N, unsigned Scale,
-                              SDOperand &Base, SDOperand &OffImm,
-                              SDOperand &Offset);
-  bool SelectThumbAddrModeS1(SDOperand Op, SDOperand N, SDOperand &Base,
-                             SDOperand &OffImm, SDOperand &Offset);
-  bool SelectThumbAddrModeS2(SDOperand Op, SDOperand N, SDOperand &Base,
-                             SDOperand &OffImm, SDOperand &Offset);
-  bool SelectThumbAddrModeS4(SDOperand Op, SDOperand N, SDOperand &Base,
-                             SDOperand &OffImm, SDOperand &Offset);
-  bool SelectThumbAddrModeSP(SDOperand Op, SDOperand N, SDOperand &Base,
-                             SDOperand &OffImm);
-
-  bool SelectShifterOperandReg(SDOperand Op, SDOperand N, SDOperand &A,
-                               SDOperand &B, SDOperand &C);
+  bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
+                       SDValue &Offset, SDValue &Opc);
+  bool SelectAddrMode2Offset(SDValue Op, SDValue N,
+                             SDValue &Offset, SDValue &Opc);
+  bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
+                       SDValue &Offset, SDValue &Opc);
+  bool SelectAddrMode3Offset(SDValue Op, SDValue N,
+                             SDValue &Offset, SDValue &Opc);
+  bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
+                       SDValue &Offset);
+
+  bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
+                         SDValue &Label);
+
+  bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
+                             SDValue &Offset);
+  bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
+                              SDValue &Base, SDValue &OffImm,
+                              SDValue &Offset);
+  bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
+                             SDValue &OffImm, SDValue &Offset);
+  bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
+                             SDValue &OffImm, SDValue &Offset);
+  bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
+                             SDValue &OffImm, SDValue &Offset);
+  bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
+                             SDValue &OffImm);
+
+  bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
+                               SDValue &B, SDValue &C);
   
   // Include the pieces autogenerated from the target description.
 #include "ARMGenDAGISel.inc"
@@ -98,9 +98,9 @@ void ARMDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
   DAG.RemoveDeadNodes();
 }
 
-bool ARMDAGToDAGISel::SelectAddrMode2(SDOperand Op, SDOperand N,
-                                      SDOperand &Base, SDOperand &Offset,
-                                      SDOperand &Opc) {
+bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
+                                      SDValue &Base, SDValue &Offset,
+                                      SDValue &Opc) {
   if (N.getOpcode() == ISD::MUL) {
     if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
       // X * [3,5,9] -> X + X * [2,4,8] etc.
@@ -206,8 +206,8 @@ bool ARMDAGToDAGISel::SelectAddrMode2(SDOperand Op, SDOperand N,
   return true;
 }
 
-bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDOperand Op, SDOperand N,
-                                            SDOperand &Offset, SDOperand &Opc) {
+bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
+                                            SDValue &Offset, SDValue &Opc) {
   unsigned Opcode = Op.getOpcode();
   ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
     ? cast<LoadSDNode>(Op)->getAddressingMode()
@@ -245,9 +245,9 @@ bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDOperand Op, SDOperand N,
 }
 
 
-bool ARMDAGToDAGISel::SelectAddrMode3(SDOperand Op, SDOperand N,
-                                      SDOperand &Base, SDOperand &Offset,
-                                      SDOperand &Opc) {
+bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
+                                      SDValue &Base, SDValue &Offset,
+                                      SDValue &Opc) {
   if (N.getOpcode() == ISD::SUB) {
     // X - C  is canonicalize to X + -C, no need to handle it here.
     Base = N.getOperand(0);
@@ -295,8 +295,8 @@ bool ARMDAGToDAGISel::SelectAddrMode3(SDOperand Op, SDOperand N,
   return true;
 }
 
-bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDOperand Op, SDOperand N,
-                                            SDOperand &Offset, SDOperand &Opc) {
+bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
+                                            SDValue &Offset, SDValue &Opc) {
   unsigned Opcode = Op.getOpcode();
   ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
     ? cast<LoadSDNode>(Op)->getAddressingMode()
@@ -318,8 +318,8 @@ bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDOperand Op, SDOperand N,
 }
 
 
-bool ARMDAGToDAGISel::SelectAddrMode5(SDOperand Op, SDOperand N,
-                                      SDOperand &Base, SDOperand &Offset) {
+bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
+                                      SDValue &Base, SDValue &Offset) {
   if (N.getOpcode() != ISD::ADD) {
     Base = N;
     if (N.getOpcode() == ISD::FrameIndex) {
@@ -364,11 +364,11 @@ bool ARMDAGToDAGISel::SelectAddrMode5(SDOperand Op, SDOperand N,
   return true;
 }
 
-bool ARMDAGToDAGISel::SelectAddrModePC(SDOperand Op, SDOperand N,
-                                        SDOperand &Offset, SDOperand &Label) {
+bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
+                                        SDValue &Offset, SDValue &Label) {
   if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
     Offset = N.getOperand(0);
-    SDOperand N1 = N.getOperand(1);
+    SDValue N1 = N.getOperand(1);
     Label  = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getValue(),
                                        MVT::i32);
     return true;
@@ -376,14 +376,14 @@ bool ARMDAGToDAGISel::SelectAddrModePC(SDOperand Op, SDOperand N,
   return false;
 }
 
-bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDOperand Op, SDOperand N,
-                                            SDOperand &Base, SDOperand &Offset){
+bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
+                                            SDValue &Base, SDValue &Offset){
   if (N.getOpcode() != ISD::ADD) {
     Base = N;
     // We must materialize a zero in a reg! Returning an constant here won't
     // work since its node is -1 so it won't get added to the selection queue.
     // Explicitly issue a tMOVri8 node!
-    Offset = SDOperand(CurDAG->getTargetNode(ARM::tMOVi8, MVT::i32,
+    Offset = SDValue(CurDAG->getTargetNode(ARM::tMOVi8, MVT::i32,
                                     CurDAG->getTargetConstant(0, MVT::i32)), 0);
     return true;
   }
@@ -394,11 +394,11 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDOperand Op, SDOperand N,
 }
 
 bool
-ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDOperand Op, SDOperand N,
-                                        unsigned Scale, SDOperand &Base,
-                                        SDOperand &OffImm, SDOperand &Offset) {
+ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
+                                        unsigned Scale, SDValue &Base,
+                                        SDValue &OffImm, SDValue &Offset) {
   if (Scale == 4) {
-    SDOperand TmpBase, TmpOffImm;
+    SDValue TmpBase, TmpOffImm;
     if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
       return false;  // We want to select tLDRspi / tSTRspi instead.
     if (N.getOpcode() == ARMISD::Wrapper &&
@@ -444,26 +444,26 @@ ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDOperand Op, SDOperand N,
   return true;
 }
 
-bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDOperand Op, SDOperand N,
-                                            SDOperand &Base, SDOperand &OffImm,
-                                            SDOperand &Offset) {
+bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
+                                            SDValue &Base, SDValue &OffImm,
+                                            SDValue &Offset) {
   return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
 }
 
-bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDOperand Op, SDOperand N,
-                                            SDOperand &Base, SDOperand &OffImm,
-                                            SDOperand &Offset) {
+bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
+                                            SDValue &Base, SDValue &OffImm,
+                                            SDValue &Offset) {
   return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
 }
 
-bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDOperand Op, SDOperand N,
-                                            SDOperand &Base, SDOperand &OffImm,
-                                            SDOperand &Offset) {
+bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
+                                            SDValue &Base, SDValue &OffImm,
+                                            SDValue &Offset) {
   return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
 }
 
-bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDOperand Op, SDOperand N,
-                                           SDOperand &Base, SDOperand &OffImm) {
+bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
+                                           SDValue &Base, SDValue &OffImm) {
   if (N.getOpcode() == ISD::FrameIndex) {
     int FI = cast<FrameIndexSDNode>(N)->getIndex();
     Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
@@ -498,11 +498,11 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDOperand Op, SDOperand N,
   return false;
 }
 
-bool ARMDAGToDAGISel::SelectShifterOperandReg(SDOperand Op,
-                                              SDOperand N, 
-                                              SDOperand &BaseReg,
-                                              SDOperand &ShReg,
-                                              SDOperand &Opc) {
+bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
+                                              SDValue N, 
+                                              SDValue &BaseReg,
+                                              SDValue &ShReg,
+                                              SDValue &Opc) {
   ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
 
   // Don't match base register only case. That is matched to a separate
@@ -523,12 +523,12 @@ bool ARMDAGToDAGISel::SelectShifterOperandReg(SDOperand Op,
 }
 
 /// getAL - Returns a ARMCC::AL immediate node.
-static inline SDOperand getAL(SelectionDAG *CurDAG) {
+static inline SDValue getAL(SelectionDAG *CurDAG) {
   return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
 }
 
 
-SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
+SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
   SDNode *N = Op.Val;
 
   if (N->isMachineOpcode())
@@ -548,7 +548,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
                ARM_AM::getSOImmVal(~Val) == -1 &&    // MVN
                !ARM_AM::isSOImmTwoPartVal(Val));     // two instrs.
     if (UseCP) {
-      SDOperand CPIdx =
+      SDValue CPIdx =
         CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
                                       TLI.getPointerTy());
 
@@ -557,7 +557,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
         ResNode = CurDAG->getTargetNode(ARM::tLDRcp, MVT::i32, MVT::Other,
                                         CPIdx, CurDAG->getEntryNode());
       else {
-        SDOperand Ops[] = {
+        SDValue Ops[] = {
           CPIdx, 
           CurDAG->getRegister(0, MVT::i32),
           CurDAG->getTargetConstant(0, MVT::i32),
@@ -567,7 +567,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
         };
         ResNode=CurDAG->getTargetNode(ARM::LDRcp, MVT::i32, MVT::Other, Ops, 6);
       }
-      ReplaceUses(Op, SDOperand(ResNode, 0));
+      ReplaceUses(Op, SDValue(ResNode, 0));
       return NULL;
     }
       
@@ -577,12 +577,12 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
   case ISD::FrameIndex: {
     // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
     int FI = cast<FrameIndexSDNode>(N)->getIndex();
-    SDOperand TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
+    SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
     if (Subtarget->isThumb())
       return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
                                   CurDAG->getTargetConstant(0, MVT::i32));
     else {
-      SDOperand Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
+      SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
                           getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
                           CurDAG->getRegister(0, MVT::i32) };
       return CurDAG->SelectNodeTo(N, ARM::ADDri, MVT::i32, Ops, 5);
@@ -590,8 +590,8 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
   }
   case ISD::ADD: {
     // Select add sp, c to tADDhirr.
-    SDOperand N0 = Op.getOperand(0);
-    SDOperand N1 = Op.getOperand(1);
+    SDValue N0 = Op.getOperand(0);
+    SDValue N1 = Op.getOperand(1);
     RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(Op.getOperand(0));
     RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(Op.getOperand(1));
     if (LHSR && LHSR->getReg() == ARM::SP) {
@@ -612,20 +612,20 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
       unsigned RHSV = C->getValue();
       if (!RHSV) break;
       if (isPowerOf2_32(RHSV-1)) {  // 2^n+1?
-        SDOperand V = Op.getOperand(0);
+        SDValue V = Op.getOperand(0);
         AddToISelQueue(V);
         unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1));
-        SDOperand Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
+        SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
                             CurDAG->getTargetConstant(ShImm, MVT::i32),
                             getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
                             CurDAG->getRegister(0, MVT::i32) };
         return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
       }
       if (isPowerOf2_32(RHSV+1)) {  // 2^n-1?
-        SDOperand V = Op.getOperand(0);
+        SDValue V = Op.getOperand(0);
         AddToISelQueue(V);
         unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV+1));
-        SDOperand Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
+        SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
                             CurDAG->getTargetConstant(ShImm, MVT::i32),
                             getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
                             CurDAG->getRegister(0, MVT::i32) };
@@ -641,7 +641,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
   case ISD::UMUL_LOHI: {
     AddToISelQueue(Op.getOperand(0));
     AddToISelQueue(Op.getOperand(1));
-    SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1),
+    SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
                         getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
                         CurDAG->getRegister(0, MVT::i32) };
     return CurDAG->getTargetNode(ARM::UMULL, MVT::i32, MVT::i32, Ops, 5);
@@ -649,7 +649,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
   case ISD::SMUL_LOHI: {
     AddToISelQueue(Op.getOperand(0));
     AddToISelQueue(Op.getOperand(1));
-    SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1),
+    SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
                         getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
                         CurDAG->getRegister(0, MVT::i32) };
     return CurDAG->getTargetNode(ARM::SMULL, MVT::i32, MVT::i32, Ops, 5);
@@ -659,7 +659,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
     ISD::MemIndexedMode AM = LD->getAddressingMode();
     MVT LoadedVT = LD->getMemoryVT();
     if (AM != ISD::UNINDEXED) {
-      SDOperand Offset, AMOpc;
+      SDValue Offset, AMOpc;
       bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
       unsigned Opcode = 0;
       bool Match = false;
@@ -688,12 +688,12 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
       }
 
       if (Match) {
-        SDOperand Chain = LD->getChain();
-        SDOperand Base = LD->getBasePtr();
+        SDValue Chain = LD->getChain();
+        SDValue Base = LD->getBasePtr();
         AddToISelQueue(Chain);
         AddToISelQueue(Base);
         AddToISelQueue(Offset);
-        SDOperand Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
+        SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
                            CurDAG->getRegister(0, MVT::i32), Chain };
         return CurDAG->getTargetNode(Opcode, MVT::i32, MVT::i32,
                                      MVT::Other, Ops, 6);
@@ -712,11 +712,11 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
     // Pattern complexity = 6  cost = 1  size = 0
 
     unsigned Opc = Subtarget->isThumb() ? ARM::tBcc : ARM::Bcc;
-    SDOperand Chain = Op.getOperand(0);
-    SDOperand N1 = Op.getOperand(1);
-    SDOperand N2 = Op.getOperand(2);
-    SDOperand N3 = Op.getOperand(3);
-    SDOperand InFlag = Op.getOperand(4);
+    SDValue Chain = Op.getOperand(0);
+    SDValue N1 = Op.getOperand(1);
+    SDValue N2 = Op.getOperand(2);
+    SDValue N3 = Op.getOperand(3);
+    SDValue InFlag = Op.getOperand(4);
     assert(N1.getOpcode() == ISD::BasicBlock);
     assert(N2.getOpcode() == ISD::Constant);
     assert(N3.getOpcode() == ISD::Register);
@@ -724,35 +724,35 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
     AddToISelQueue(Chain);
     AddToISelQueue(N1);
     AddToISelQueue(InFlag);
-    SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
+    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
                                cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
-    SDOperand Ops[] = { N1, Tmp2, N3, Chain, InFlag };
+    SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
     SDNode *ResNode = CurDAG->getTargetNode(Opc, MVT::Other, MVT::Flag, Ops, 5);
-    Chain = SDOperand(ResNode, 0);
+    Chain = SDValue(ResNode, 0);
     if (Op.Val->getNumValues() == 2) {
-      InFlag = SDOperand(ResNode, 1);
-      ReplaceUses(SDOperand(Op.Val, 1), InFlag);
+      InFlag = SDValue(ResNode, 1);
+      ReplaceUses(SDValue(Op.Val, 1), InFlag);
     }
-    ReplaceUses(SDOperand(Op.Val, 0), SDOperand(Chain.Val, Chain.ResNo));
+    ReplaceUses(SDValue(Op.Val, 0), SDValue(Chain.Val, Chain.ResNo));
     return NULL;
   }
   case ARMISD::CMOV: {
     bool isThumb = Subtarget->isThumb();
     MVT VT = Op.getValueType();
-    SDOperand N0 = Op.getOperand(0);
-    SDOperand N1 = Op.getOperand(1);
-    SDOperand N2 = Op.getOperand(2);
-    SDOperand N3 = Op.getOperand(3);
-    SDOperand InFlag = Op.getOperand(4);
+    SDValue N0 = Op.getOperand(0);
+    SDValue N1 = Op.getOperand(1);
+    SDValue N2 = Op.getOperand(2);
+    SDValue N3 = Op.getOperand(3);
+    SDValue InFlag = Op.getOperand(4);
     assert(N2.getOpcode() == ISD::Constant);
     assert(N3.getOpcode() == ISD::Register);
 
     // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
     // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
     // Pattern complexity = 18  cost = 1  size = 0
-    SDOperand CPTmp0;
-    SDOperand CPTmp1;
-    SDOperand CPTmp2;
+    SDValue CPTmp0;
+    SDValue CPTmp1;
+    SDValue CPTmp2;
     if (!isThumb && VT == MVT::i32 &&
         SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
       AddToISelQueue(N0);
@@ -760,9 +760,9 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
       AddToISelQueue(CPTmp1);
       AddToISelQueue(CPTmp2);
       AddToISelQueue(InFlag);
-      SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
+      SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
                                cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
-      SDOperand Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
+      SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
       return CurDAG->SelectNodeTo(Op.Val, ARM::MOVCCs, MVT::i32, Ops, 7);
     }
 
@@ -777,12 +777,12 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
         Predicate_so_imm(N3.Val)) {
       AddToISelQueue(N0);
       AddToISelQueue(InFlag);
-      SDOperand Tmp1 = CurDAG->getTargetConstant(((unsigned)
+      SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
                                cast<ConstantSDNode>(N1)->getValue()), MVT::i32);
       Tmp1 = Transform_so_imm_XFORM(Tmp1.Val);
-      SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
+      SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
                                cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
-      SDOperand Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
+      SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
       return CurDAG->SelectNodeTo(Op.Val, ARM::MOVCCi, MVT::i32, Ops, 5);
     }
 
@@ -798,9 +798,9 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
     AddToISelQueue(N0);
     AddToISelQueue(N1);
     AddToISelQueue(InFlag);
-    SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
+    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
                                cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
-    SDOperand Ops[] = { N0, N1, Tmp2, N3, InFlag };
+    SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
     unsigned Opc = 0;
     switch (VT.getSimpleVT()) {
     default: assert(false && "Illegal conditional move type!");
@@ -819,20 +819,20 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
   }
   case ARMISD::CNEG: {
     MVT VT = Op.getValueType();
-    SDOperand N0 = Op.getOperand(0);
-    SDOperand N1 = Op.getOperand(1);
-    SDOperand N2 = Op.getOperand(2);
-    SDOperand N3 = Op.getOperand(3);
-    SDOperand InFlag = Op.getOperand(4);
+    SDValue N0 = Op.getOperand(0);
+    SDValue N1 = Op.getOperand(1);
+    SDValue N2 = Op.getOperand(2);
+    SDValue N3 = Op.getOperand(3);
+    SDValue InFlag = Op.getOperand(4);
     assert(N2.getOpcode() == ISD::Constant);
     assert(N3.getOpcode() == ISD::Register);
 
     AddToISelQueue(N0);
     AddToISelQueue(N1);
     AddToISelQueue(InFlag);
-    SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
+    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
                                cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
-    SDOperand Ops[] = { N0, N1, Tmp2, N3, InFlag };
+    SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
     unsigned Opc = 0;
     switch (VT.getSimpleVT()) {
     default: assert(false && "Illegal conditional move type!");
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index afc7ebc4c9..c696832fda 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -399,13 +399,13 @@ HowToPassArgument(MVT ObjectVT, unsigned NumGPRs,
 /// LowerCALL - Lowering a ISD::CALL node into a callseq_start <-
 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
 /// nodes.
-SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
+SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
   MVT RetVT= Op.Val->getValueType(0);
-  SDOperand Chain    = Op.getOperand(0);
+  SDValue Chain    = Op.getOperand(0);
   unsigned CallConv  = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
   assert((CallConv == CallingConv::C ||
           CallConv == CallingConv::Fast) && "unknown calling convention");
-  SDOperand Callee   = Op.getOperand(4);
+  SDValue Callee   = Op.getOperand(4);
   unsigned NumOps    = (Op.getNumOperands() - 5) / 2;
   unsigned ArgOffset = 0;   // Frame mechanisms handle retaddr slot
   unsigned NumGPRs = 0;     // GPRs used for parameter passing.
@@ -433,17 +433,17 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
   Chain = DAG.getCALLSEQ_START(Chain,
                                DAG.getConstant(NumBytes, MVT::i32));
 
-  SDOperand StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
+  SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
 
   static const unsigned GPRArgRegs[] = {
     ARM::R0, ARM::R1, ARM::R2, ARM::R3
   };
 
   NumGPRs = 0;
-  std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
-  std::vector<SDOperand> MemOpChains;
+  std::vector<std::pair<unsigned, SDValue> > RegsToPass;
+  std::vector<SDValue> MemOpChains;
   for (unsigned i = 0; i != NumOps; ++i) {
-    SDOperand Arg = Op.getOperand(5+2*i);
+    SDValue Arg = Op.getOperand(5+2*i);
     ISD::ArgFlagsTy Flags =
       cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags();
     MVT ArgVT = Arg.getValueType();
@@ -467,22 +467,22 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
                                  DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg)));
         break;
       case MVT::i64: {
-        SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
+        SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
                                    DAG.getConstant(0, getPointerTy()));
-        SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
+        SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
                                    DAG.getConstant(1, getPointerTy()));
         RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo));
         if (ObjGPRs == 2)
           RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi));
         else {
-          SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
+          SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
           PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
           MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0));
         }
         break;
       }
       case MVT::f64: {
-        SDOperand Cvt = DAG.getNode(ARMISD::FMRRD,
+        SDValue Cvt = DAG.getNode(ARMISD::FMRRD,