Eliminate all remaining tabs and trailing spaces.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22523 91177308-0d34-0410-b5e6-96231b3b80d8

39 files changed, 931 insertions, 931 deletions

diff --git a/lib/Target/Alpha/AlphaCodeEmitter.cpp b/lib/Target/Alpha/AlphaCodeEmitter.cpp
index 92e38b93cd..cea0fe8982 100644
--- a/lib/Target/Alpha/AlphaCodeEmitter.cpp
+++ b/lib/Target/Alpha/AlphaCodeEmitter.cpp
@@ -169,11 +169,11 @@ int AlphaCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
     rv = getAlphaRegNumber(MO.getReg());
   } else if (MO.isImmediate()) {
     rv = MO.getImmedValue();
-  } else if (MO.isGlobalAddress() || MO.isExternalSymbol() 
+  } else if (MO.isGlobalAddress() || MO.isExternalSymbol()
              || MO.isConstantPoolIndex()) {
     DEBUG(std::cerr << MO << " is a relocated op for " << MI << "\n";);
-    bool isExternal = MO.isExternalSymbol() || 
-      (MO.isGlobalAddress() && 
+    bool isExternal = MO.isExternalSymbol() ||
+      (MO.isGlobalAddress() &&
        ( MO.getGlobal()->hasWeakLinkage() ||
          MO.getGlobal()->isExternal()) );
     unsigned Reloc = 0;
@@ -213,7 +213,7 @@ int AlphaCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
                                           true));
     else
       MCE.addRelocation(MachineRelocation((unsigned)MCE.getCurrentPCOffset(),
-                                          Reloc, MO.getConstantPoolIndex(), 
+                                          Reloc, MO.getConstantPoolIndex(),
                                           Offset));
   } else if (MO.isMachineBasicBlock()) {
     unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 6d5dbeafc8..e3c5c4ba40 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -64,7 +64,7 @@ namespace {
       //Move an Ireg to a FPreg
       ITOF,
       //Move a  FPreg to an Ireg
-      FTOI, 
+      FTOI,
     };
   }
 }
@@ -93,7 +93,7 @@ namespace {
 
       setOperationAction(ISD::EXTLOAD, MVT::i1,  Promote);
       setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
- 
+
       setOperationAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
       setOperationAction(ISD::ZEXTLOAD, MVT::i32, Expand);
 
@@ -164,7 +164,7 @@ namespace {
     virtual std::pair<SDOperand,SDOperand>
       LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
                  const Type *ArgTy, SelectionDAG &DAG);
-    
+
     void restoreGP(MachineBasicBlock* BB)
     {
       BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP);
@@ -203,8 +203,8 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
         } else {
           int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
           SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
-          SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, 
-                                        DAG.getEntryNode(), Op.getOperand(0), 
+          SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other,
+                                        DAG.getEntryNode(), Op.getOperand(0),
                                         StackSlot, DAG.getSrcValue(NULL));
           SRC = DAG.getLoad(Op.getValueType(), Store.getValue(0), StackSlot,
                             DAG.getSrcValue(NULL));
@@ -289,7 +289,7 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
       case MVT::i16:
       case MVT::i32:
       case MVT::i64:
-        args_int[count] = AddLiveIn(MF, args_int[count], 
+        args_int[count] = AddLiveIn(MF, args_int[count],
                                     getRegClassFor(MVT::i64));
         argt = DAG.getCopyFromReg(args_int[count], VT, DAG.getRoot());
         if (VT != MVT::i64)
@@ -322,15 +322,15 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
       int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
       if (i == 0) VarArgsBase = FI;
       SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
-      LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt, 
+      LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
                                SDFI, DAG.getSrcValue(NULL)));
-      
+
       if (args_float[i] < 1024)
         args_float[i] = AddLiveIn(MF,args_float[i], getRegClassFor(MVT::f64));
       argt = DAG.getCopyFromReg(args_float[i], MVT::f64, DAG.getRoot());
       FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
       SDFI = DAG.getFrameIndex(FI, MVT::i64);
-      LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt, 
+      LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
                                SDFI, DAG.getSrcValue(NULL)));
     }
 
@@ -363,7 +363,7 @@ std::pair<SDOperand, SDOperand>
 AlphaTargetLowering::LowerCallTo(SDOperand Chain,
                                  const Type *RetTy, bool isVarArg,
                                  unsigned CallingConv, bool isTailCall,
-                                 SDOperand Callee, ArgListTy &Args, 
+                                 SDOperand Callee, ArgListTy &Args,
                                  SelectionDAG &DAG) {
   int NumBytes = 0;
   if (Args.size() > 6)
@@ -413,12 +413,12 @@ SDOperand AlphaTargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
                                             Value *VAListV, SelectionDAG &DAG) {
   // vastart stores the address of the VarArgsBase and VarArgsOffset
   SDOperand FR  = DAG.getFrameIndex(VarArgsBase, MVT::i64);
-  SDOperand S1  = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP, 
+  SDOperand S1  = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
                               DAG.getSrcValue(VAListV));
-  SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP, 
+  SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
                               DAG.getConstant(8, MVT::i64));
-  return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1, 
-                     DAG.getConstant(VarArgsOffset, MVT::i64), SA2, 
+  return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1,
+                     DAG.getConstant(VarArgsOffset, MVT::i64), SA2,
                      DAG.getSrcValue(VAListV, 8), DAG.getValueType(MVT::i32));
 }
 
@@ -427,9 +427,9 @@ LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
            const Type *ArgTy, SelectionDAG &DAG) {
   SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP,
                                DAG.getSrcValue(VAListV));
-  SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP, 
+  SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
                               DAG.getConstant(8, MVT::i64));
-  SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1), 
+  SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
                                     Tmp, DAG.getSrcValue(VAListV, 8), MVT::i32);
   SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
   if (ArgTy->isFloatingPoint())
@@ -437,7 +437,7 @@ LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
     //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
       SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
                                         DAG.getConstant(8*6, MVT::i64));
-      SDOperand CC = DAG.getSetCC(ISD::SETLT, MVT::i64, 
+      SDOperand CC = DAG.getSetCC(ISD::SETLT, MVT::i64,
                                   Offset, DAG.getConstant(8*6, MVT::i64));
       DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
   }
@@ -450,13 +450,13 @@ LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
     Result = DAG.getExtLoad(ISD::ZEXTLOAD, MVT::i64, Offset.getValue(1),
                             DataPtr, DAG.getSrcValue(NULL), MVT::i32);
   else
-    Result = DAG.getLoad(getValueType(ArgTy), Offset.getValue(1), DataPtr, 
+    Result = DAG.getLoad(getValueType(ArgTy), Offset.getValue(1), DataPtr,
                          DAG.getSrcValue(NULL));
 
-  SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset, 
+  SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
                                     DAG.getConstant(8, MVT::i64));
-  SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, 
-                                 Result.getValue(1), NewOffset, 
+  SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other,
+                                 Result.getValue(1), NewOffset,
                                  Tmp, DAG.getSrcValue(VAListV, 8),
                                  DAG.getValueType(MVT::i32));
   Result = DAG.getNode(ISD::TRUNCATE, getValueType(ArgTy), Result);
@@ -468,15 +468,15 @@ LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
 SDOperand AlphaTargetLowering::
 LowerVACopy(SDOperand Chain, SDOperand SrcP, Value *SrcV, SDOperand DestP,
             Value *DestV, SelectionDAG &DAG) {
-  SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, 
+  SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP,
                               DAG.getSrcValue(SrcV));
   SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
                                  Val, DestP, DAG.getSrcValue(DestV));
-  SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP, 
+  SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
                              DAG.getConstant(8, MVT::i64));
   Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP,
                        DAG.getSrcValue(SrcV, 8), MVT::i32);
-  SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP, 
+  SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
                              DAG.getConstant(8, MVT::i64));
   return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1),
                      Val, NPD, DAG.getSrcValue(DestV, 8),
@@ -514,7 +514,7 @@ class AlphaISel : public SelectionDAGISel {
   int max_depth;
 
 public:
-  AlphaISel(TargetMachine &TM) : SelectionDAGISel(AlphaLowering), 
+  AlphaISel(TargetMachine &TM) : SelectionDAGISel(AlphaLowering),
     AlphaLowering(TM)
   {}
 
@@ -535,9 +535,9 @@ public:
     if(has_sym)
       ++count_ins;
     if(EnableAlphaCount)
-      std::cerr << "COUNT: " 
-                << BB->getParent()->getFunction ()->getName() << " " 
-                << BB->getNumber() << " " 
+      std::cerr << "COUNT: "
+                << BB->getParent()->getFunction ()->getName() << " "
+                << BB->getNumber() << " "
                 << max_depth << " "
                 << count_ins << " "
                 << count_outs << "\n";
@@ -546,7 +546,7 @@ public:
     ExprMap.clear();
     CCInvMap.clear();
   }
-  
+
   virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
 
   unsigned SelectExpr(SDOperand N);
@@ -1032,7 +1032,7 @@ void AlphaISel::SelectBranchCC(SDOperand N)
         return;
       }
     } else { //FP
-      //Any comparison between 2 values should be codegened as an folded 
+      //Any comparison between 2 values should be codegened as an folded
       //branch, as moving CC to the integer register is very expensive
       //for a cmp b: c = a - b;
       //a = b: c = 0
@@ -1298,7 +1298,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
   case ISD::GlobalAddress:
     AlphaLowering.restoreGP(BB);
     has_sym = true;
- 
+
     Reg = Result = MakeReg(MVT::i64);
 
     if (EnableAlphaLSMark)
@@ -1559,7 +1559,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
 
           switch (SetCC->getCondition()) {
           default: Node->dump(); assert(0 && "Unknown integer comparison!");
-          case ISD::SETEQ: 
+          case ISD::SETEQ:
             Opc = isConst ? Alpha::CMPEQi : Alpha::CMPEQ; dir=1; break;
           case ISD::SETLT:
             Opc = isConst ? Alpha::CMPLTi : Alpha::CMPLT; dir = 1; break;
@@ -1675,7 +1675,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
     //Check operand(0) == Not
     if (N.getOperand(0).getOpcode() == ISD::XOR &&
         N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
-        cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getSignExtended() 
+        cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getSignExtended()
         == -1) {
       switch(opcode) {
         case ISD::AND: Opc = Alpha::BIC; break;
@@ -1730,8 +1730,8 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
       case ISD::SHL: Opc = Alpha::SL; break;
       case ISD::SRL: Opc = Alpha::SRL; break;
       case ISD::SRA: Opc = Alpha::SRA; break;
-      case ISD::MUL: 
-        Opc = isFP ? (DestType == MVT::f64 ? Alpha::MULT : Alpha::MULS) 
+      case ISD::MUL:
+        Opc = isFP ? (DestType == MVT::f64 ? Alpha::MULT : Alpha::MULS)
           : Alpha::MULQ;
         break;
       };
@@ -1807,7 +1807,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
       }
       else if((CSD = dyn_cast<ConstantSDNode>(N.getOperand(1))) &&
               (int64_t)CSD->getValue() >= 255 &&
-              (int64_t)CSD->getValue() <= 0)              
+              (int64_t)CSD->getValue() <= 0)
       { //inverted imm add/sub
         Opc = isAdd ? Alpha::SUBQi : Alpha::ADDQi;
         Tmp1 = SelectExpr(N.getOperand(0));
@@ -1903,7 +1903,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
     }
     Tmp1 = SelectExpr(N.getOperand(0));
     Tmp2 = SelectExpr(N.getOperand(1));
-    SDOperand Addr = 
+    SDOperand Addr =
       ISelDAG->getExternalSymbol(opstr, AlphaLowering.getPointerTy());
     Tmp3 = SelectExpr(Addr);
     //set up regs explicitly (helps Reg alloc)
@@ -1947,7 +1947,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
       if (SetCC && !MVT::isInteger(SetCC->getOperand(0).getValueType()))
       { //FP Setcc -> Select yay!
 
-        
+
         //for a cmp b: c = a - b;
         //a = b: c = 0
         //a < b: c < 0
@@ -2000,7 +2000,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
 //         // Get the condition into the zero flag.
 //         BuildMI(BB, Alpha::FCMOVEQ, 3, Result).addReg(TV).addReg(FV).addReg(Tmp4);
         return Result;
-      }  
+      }
     } else {
       //FIXME: look at parent to decide if intCC can be folded, or if setCC(FP)
       //and can save stack use
@@ -2116,7 +2116,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
         //re-get the val since we are going to mem anyway
         val = (int64_t)cast<ConstantSDNode>(N)->getValue();
         MachineConstantPool *CP = BB->getParent()->getConstantPool();
-        ConstantUInt *C = 
+        ConstantUInt *C =
           ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , val);
         unsigned CPI = CP->getConstantPoolIndex(C);
         AlphaLowering.restoreGP(BB);
@@ -2317,8 +2317,8 @@ void AlphaISel::Select(SDOperand N) {
       }
 
       int i, j, k;
-      if (EnableAlphaLSMark) 
-        getValueInfo(cast<SrcValueSDNode>(N.getOperand(3))->getValue(), 
+      if (EnableAlphaLSMark)
+        getValueInfo(cast<SrcValueSDNode>(N.getOperand(3))->getValue(),
                      i, j, k);
 
       GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(Address);
diff --git a/lib/Target/Alpha/AlphaJITInfo.cpp b/lib/Target/Alpha/AlphaJITInfo.cpp
index c2074ff061..5217842964 100644
--- a/lib/Target/Alpha/AlphaJITInfo.cpp
+++ b/lib/Target/Alpha/AlphaJITInfo.cpp
@@ -59,7 +59,7 @@ extern "C" {
     void* CameFromOrig = (void*)*(oldsp - 2);
 
     void* Target = JITCompilerFunction(CameFromStub);
-    
+
     //rewrite the stub to an unconditional branch
     EmitBranchToAt(CameFromStub, Target, false);
 
@@ -256,7 +256,7 @@ void AlphaJITInfo::relocate(void *Function, MachineRelocation *MR,
       case 0x08: //LDA
         assert(gpdistmap[make_pair(Function, MR->getConstantVal())] &&
                "LDAg without seeing LDAHg");
-        idx = &GOTBase[GOToffset * 8] - 
+        idx = &GOTBase[GOToffset * 8] -
           (unsigned char*)gpdistmap[make_pair(Function, MR->getConstantVal())];
         idx = getLower16(idx);
         DEBUG(std::cerr << "LDA: " << idx << "\n");
diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp
index 7d19da4c0f..ab6bb2c939 100644
--- a/lib/Target/IA64/IA64ISelPattern.cpp
+++ b/lib/Target/IA64/IA64ISelPattern.cpp
@@ -226,7 +226,7 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
         // Create the frame index object for this incoming parameter...
         ArgOffset = 16 + 8 * (count - 8);
         int FI = MFI->CreateFixedObject(8, ArgOffset);
-        
+
         // Create the SelectionDAG nodes corresponding to a load
         //from this parameter
         SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
@@ -307,7 +307,7 @@ std::pair<SDOperand, SDOperand>
 IA64TargetLowering::LowerCallTo(SDOperand Chain,
                                 const Type *RetTy, bool isVarArg,
                                 unsigned CallingConv, bool isTailCall,
-                                SDOperand Callee, ArgListTy &Args, 
+                                SDOperand Callee, ArgListTy &Args,
                                 SelectionDAG &DAG) {
 
   MachineFunction &MF = DAG.getMachineFunction();
@@ -400,7 +400,7 @@ LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
            "Other types should have been promoted for varargs!");
     Amt = 8;
   }
-  Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val, 
+  Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
                     DAG.getConstant(Amt, Val.getValueType()));
   Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
                       Val, VAListP, DAG.getSrcValue(VAListV));
@@ -494,22 +494,22 @@ void boothEncode(std::string inString, std::string& boothEncodedString) {
   int lim=inString.size();
 
   while(curpos<lim) {
-    if(inString[curpos]=='1') { // if we see a '1', look for a run of them 
+    if(inString[curpos]=='1') { // if we see a '1', look for a run of them
       int runlength=0;
       std::string replaceString="N";
-     
+
       // find the run length
       for(;inString[curpos+runlength]=='1';runlength++) ;
 
       for(int i=0; i<runlength-1; i++)
-	replaceString+="0";
+        replaceString+="0";
       replaceString+="1";
 
       if(runlength>1) {
-	inString.replace(curpos, runlength+1, replaceString);
-	curpos+=runlength-1;
+        inString.replace(curpos, runlength+1, replaceString);
+        curpos+=runlength-1;
       } else
-	curpos++;
+        curpos++;
     } else { // a zero, we just keep chugging along
       curpos++;
     }
@@ -529,7 +529,7 @@ void boothEncode(std::string inString, std::string& boothEncodedString) {
 
 struct shiftaddblob { // this encodes stuff like (x=) "A << B [+-] C << D"
   unsigned firstVal;    // A
-  unsigned firstShift;  // B 
+  unsigned firstShift;  // B
   unsigned secondVal;   // C
   unsigned secondShift; // D
   bool isSub;
@@ -555,7 +555,7 @@ unsigned lefevre(const std::string inString,
   }
 
   std::vector<int> p,n;
-  
+
   for(int i=0; i<=length; i++) {
     if (s.c_str()[length-i]=='P') {
       p.push_back(i);
@@ -609,49 +609,49 @@ unsigned lefevre(const std::string inString,
     int z=abs(int_d)-1;
 
     if(int_d>0) {
-      
+
       for(unsigned base=0; base<retstring.size(); base++) {
-	if( ((base+z+1) < retstring.size()) &&
-	   retstring.c_str()[base]=='P' &&
-	   retstring.c_str()[base+z+1]=='P')
-	{
-	  // match
-	  x++;
-	  retstring.replace(base, 1, "0");
-	  retstring.replace(base+z+1, 1, "p");
-	}
+        if( ((base+z+1) < retstring.size()) &&
+           retstring.c_str()[base]=='P' &&
+           retstring.c_str()[base+z+1]=='P')
+        {
+          // match
+          x++;
+          retstring.replace(base, 1, "0");
+          retstring.replace(base+z+1, 1, "p");
+        }
       }
 
       for(unsigned base=0; base<retstring.size(); base++) {
-	if( ((base+z+1) < retstring.size()) &&
-	   retstring.c_str()[base]=='N' &&
-	   retstring.c_str()[base+z+1]=='N')
-	{
-	  // match
-	  x++;
-	  retstring.replace(base, 1, "0");
-	  retstring.replace(base+z+1, 1, "n");
-	}
+        if( ((base+z+1) < retstring.size()) &&
+           retstring.c_str()[base]=='N' &&
+           retstring.c_str()[base+z+1]=='N')
+        {
+          // match
+          x++;
+          retstring.replace(base, 1, "0");
+          retstring.replace(base+z+1, 1, "n");
+        }
       }
 
     } else {
       for(unsigned base=0; base<retstring.size(); base++) {
-	if( ((base+z+1) < retstring.size()) &&
-	    ((retstring.c_str()[base]=='P' &&
-	     retstring.c_str()[base+z+1]=='N') ||
-	    (retstring.c_str()[base]=='N' &&
-	     retstring.c_str()[base+z+1]=='P')) ) {
-	  // match
-	  x++;
-	  
-	  if(retstring.c_str()[base]=='P') {
-	    retstring.replace(base, 1, "0");
-	    retstring.replace(base+z+1, 1, "p");
-	  } else { // retstring[base]=='N'
-	    retstring.replace(base, 1, "0");
-	    retstring.replace(base+z+1, 1, "n");
-	  }
-	}
+        if( ((base+z+1) < retstring.size()) &&
+            ((retstring.c_str()[base]=='P' &&
+             retstring.c_str()[base+z+1]=='N') ||
+            (retstring.c_str()[base]=='N' &&
+             retstring.c_str()[base+z+1]=='P')) ) {
+          // match
+          x++;
+
+          if(retstring.c_str()[base]=='P') {
+            retstring.replace(base, 1, "0");
+            retstring.replace(base+z+1, 1, "p");
+          } else { // retstring[base]=='N'
+            retstring.replace(base, 1, "0");
+            retstring.replace(base+z+1, 1, "n");
+          }
+        }
       }
     }
 
@@ -660,11 +660,11 @@ unsigned lefevre(const std::string inString,
       t = retstring;
       c = int_d; // tofix
     }
-    
+
   } d.pop_back(); // hmm
 
   u = t;
-  
+
   for(unsigned i=0; i<t.length(); i++) {
     if(t.c_str()[i]=='p' || t.c_str()[i]=='n')
       t.replace(i, 1, "0");
@@ -684,7 +684,7 @@ unsigned lefevre(const std::string inString,
     c=-c;
   } else
     f=false;
-  
+
   int pos=0;
   while(u[pos]=='0')
     pos++;
@@ -699,9 +699,9 @@ unsigned lefevre(const std::string inString,
       bool isN=(u[p]=='N');
 
       if(isP)
-	u.replace(p, 1, "N");
+        u.replace(p, 1, "N");
       if(isN)
-	u.replace(p, 1, "P");
+        u.replace(p, 1, "P");
     }
   }
 
@@ -710,7 +710,7 @@ unsigned lefevre(const std::string inString,
   int i = lefevre(u, ops);
 
   shiftaddblob blob;
-  
+
   blob.firstVal=i; blob.firstShift=c;
   blob.isSub=f;
   blob.secondVal=i; blob.secondShift=0;
@@ -731,9 +731,9 @@ unsigned lefevre(const std::string inString,
       bool isN=(t.c_str()[p]=='N');
 
       if(isP)
-	t.replace(p, 1, "N");
+        t.replace(p, 1, "N");
       if(isN)
-	t.replace(p, 1, "P");
+        t.replace(p, 1, "P");
     }
   }
 
@@ -764,7 +764,7 @@ unsigned lefevre(const std::string inString,
       break;
       //assert
   }
- 
+
   ops.push_back(blob);
   return ops.size();
 }
@@ -808,7 +808,7 @@ SDOperand ISel::BuildConstmulSequence(SDOperand N) {
 
   assert(ops.size() < 80 && "constmul code has gone haywire\n");
   SDOperand results[80]; // temporary results (of adds/subs of shifts)
-  
+
   // now turn 'ops' into DAG bits
   for(unsigned i=0; i<ops.size(); i++) {
     SDOperand amt = ISelDAG->getConstant(ops[i].firstShift, MVT::i64);
@@ -830,11 +830,11 @@ SDOperand ISel::BuildConstmulSequence(SDOperand N) {
   if(preliminaryShift) {
     SDOperand finalshift = ISelDAG->getConstant(preliminaryShift, MVT::i64);
     shiftedresult = ISelDAG->getNode(ISD::SHL, MVT::i64,
-	results[ops.size()-1], finalshift);
+        results[ops.size()-1], finalshift);
   } else { // there was no preliminary divide-by-power-of-2 required
     shiftedresult = results[ops.size()-1];
   }
- 
+
   SDOperand finalresult;
   if(flippedSign) { // if we were multiplying by a negative constant:
     SDOperand zero = ISelDAG->getConstant(0, MVT::i64);
@@ -843,8 +843,8 @@ SDOperand ISel::BuildConstmulSequence(SDOperand N) {
   } else { // there was no preliminary multiply by -1 required
     finalresult = shiftedresult;
   }
-  
-  return finalresult; 
+
+  return finalresult;
 }
 
 /// ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N.  It
@@ -1098,7 +1098,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
             .addReg(Tmp1);
           break;
       }
-      
+
       return Result;
   }
 
@@ -1316,7 +1316,7 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n");
         Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
         int shl_amt = CSD->getValue();
         Tmp3 = SelectExpr(N.getOperand(1));
-        
+
         BuildMI(BB, IA64::SHLADD, 3, Result)
           .addReg(Tmp1).addImm(shl_amt).addReg(Tmp3);
         return Result; // early exit
@@ -1344,21 +1344,21 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n");
 
     if(DestType != MVT::f64) { // TODO: speed!
       if(N.getOperand(1).getOpcode() != ISD::Constant) { // if not a const mul
-	// boring old integer multiply with xma