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authorTorok Edwin <edwintorok@gmail.com>2009-07-11 20:10:48 +0000
committerTorok Edwin <edwintorok@gmail.com>2009-07-11 20:10:48 +0000
commitc25e7581b9b8088910da31702d4ca21c4734c6d7 (patch)
treee4bb95c96a33fda5d5204f2c9d1b906084760415 /lib/Target/XCore/XCoreInstrInfo.cpp
parentd51ffcf303070b0a5aea7f365b85f6f969c384cb (diff)
assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of line. LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for NDEBUG builds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/XCoreInstrInfo.cpp')
-rw-r--r--lib/Target/XCore/XCoreInstrInfo.cpp9
1 files changed, 5 insertions, 4 deletions
diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp
index 504d2025ed..147d29d870 100644
--- a/lib/Target/XCore/XCoreInstrInfo.cpp
+++ b/lib/Target/XCore/XCoreInstrInfo.cpp
@@ -21,6 +21,7 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "XCoreGenInstrInfo.inc"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
namespace llvm {
namespace XCore {
@@ -186,7 +187,7 @@ static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
{
switch (CC) {
- default: assert(0 && "Illegal condition code!");
+ default: LLVM_UNREACHABLE("Illegal condition code!");
case XCore::COND_TRUE : return XCore::BRFT_lru6;
case XCore::COND_FALSE : return XCore::BRFF_lru6;
}
@@ -197,7 +198,7 @@ static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
{
switch (CC) {
- default: assert(0 && "Illegal condition code!");
+ default: LLVM_UNREACHABLE("Illegal condition code!");
case XCore::COND_TRUE : return XCore::COND_FALSE;
case XCore::COND_FALSE : return XCore::COND_TRUE;
}
@@ -407,7 +408,7 @@ void XCoreInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const
{
- assert(0 && "unimplemented\n");
+ LLVM_UNREACHABLE("unimplemented\n");
}
void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
@@ -427,7 +428,7 @@ void XCoreInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const
{
- assert(0 && "unimplemented\n");
+ LLVM_UNREACHABLE("unimplemented\n");
}
bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,