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| author | Evan Cheng <evan.cheng@apple.com> | 2008-05-29 08:22:04 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2008-05-29 08:22:04 +0000 |
| commit | f26ffe987cf3643a7bd66bd9f97c34605ba7d08e (patch) | |
| tree | 96ec60731614a458cd3ad8f59bd6f109d715e3f4 /lib/Target/X86/X86InstrSSE.td | |
| parent | cd5e6dda7e91af662f378e43842e6d2d55ec3057 (diff) | |
Implement vector shift up / down and insert zero with ps{rl}lq / ps{rl}ldq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51667 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrSSE.td')
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 1ea4bfd35e..3d5959aa2f 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -51,6 +51,8 @@ def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL", SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>; def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad, [SDNPHasChain, SDNPMayLoad]>; +def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>; +def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>; //===----------------------------------------------------------------------===// // SSE Complex Patterns @@ -1957,6 +1959,12 @@ let Predicates = [HasSSE2] in { (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>; def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)), (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>; + + // Shift up / down and insert zero's. + def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))), + (v2i64 (PSLLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>; + def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))), + (v2i64 (PSRLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>; } // Logical |