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authorEvan Cheng <evan.cheng@apple.com>2008-10-17 17:14:20 +0000
committerEvan Cheng <evan.cheng@apple.com>2008-10-17 17:14:20 +0000
commit4b299d4ebdf57c56ca336d9aca6f2ad7d8175995 (patch)
treed6be26dbd22d8990e94554898f4298a4c737e73e /lib/Target/X86/X86InstrSSE.td
parent244911bdeece7b45d6b75ea2b5a17f18d9ba6d95 (diff)
Fix lfence and mfence encoding. These look like MRM5r and MRM6r instructions except they do not have any operands. The RegModRM byte is encoded with register number 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57692 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrSSE.td')
-rw-r--r--lib/Target/X86/X86InstrSSE.td4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index 0a5089d1ab..426bddcea0 100644
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -2239,9 +2239,9 @@ def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
TB, Requires<[HasSSE2]>;
// Load, store, and memory fence
-def LFENCE : I<0xAE, MRM5m, (outs), (ins),
+def LFENCE : I<0xAE, MRM5r, (outs), (ins),
"lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
-def MFENCE : I<0xAE, MRM6m, (outs), (ins),
+def MFENCE : I<0xAE, MRM6r, (outs), (ins),
"mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
//TODO: custom lower this so as to never even generate the noop