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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-09-13 00:25:00 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-09-13 00:25:00 +0000 |
| commit | aa0cfea9a439cb8de1ff288bd6db9b4a86c4da7b (patch) | |
| tree | 35cd4b79ba4213d5d0d0c8c44f63fb4244c13463 /lib/Target/X86/X86InstrInfo.td | |
| parent | 253353c9cf1ff16d9c30a89c2fb96160ac5a9d65 (diff) | |
Don't fold indexed loads into TCRETURNmi64.
We don't have enough GR64_TC registers when calling a varargs function
with 6 arguments. Since %al holds the number of vector registers used,
only %r11 is available as a scratch register.
This means that addressing modes using both base and index registers
can't be folded into TCRETURNmi64.
<rdar://problem/12282281>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163761 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrInfo.td')
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index aabb442f74..b91f3c0ad4 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -543,6 +543,10 @@ def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr", def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr", [tglobaltlsaddr], []>; +// Same as addr, but reject addressing modes requiring more than one register. +def single_reg_addr : ComplexPattern<iPTR, 5, "SelectSingleRegAddr", [], + [SDNPWantParent]>; + //===----------------------------------------------------------------------===// // X86 Instruction Predicate Definitions. def HasCMov : Predicate<"Subtarget->hasCMov()">; |