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| author | Nadav Rotem <nrotem@apple.com> | 2012-08-30 19:17:29 +0000 |
|---|---|---|
| committer | Nadav Rotem <nrotem@apple.com> | 2012-08-30 19:17:29 +0000 |
| commit | e757f00446fb3c80a96d729f0530b87e9148db7f (patch) | |
| tree | 55d83fac195e0ccbd774f773fc4e650365335132 /lib/Target/X86/Disassembler/X86Disassembler.cpp | |
| parent | 62316fa00a342bdb618e4c020c8e8606f541db92 (diff) | |
Currently targets that do not support selects with scalar conditions and vector operands - scalarize the code. ARM is such a target
because it does not support CMOV of vectors. To implement this efficientlyi, we broadcast the condition bit and use a sequence of NAND-OR
to select between the two operands. This is the same sequence we use for targets that don't have vector BLENDs (like SSE2).
rdar://12201387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162926 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/Disassembler/X86Disassembler.cpp')
0 files changed, 0 insertions, 0 deletions