Sparc instruction opcodes now all live under the `V9' namespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6249 91177308-0d34-0410-b5e6-96231b3b80d8

9 files changed, 571 insertions, 570 deletions

diff --git a/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp b/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp
index cf3e5b32a3..fceb6bb8e4 100644
--- a/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp
+++ b/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp
@@ -91,7 +91,7 @@ void BBLiveVar::calcDefUseSets() {
         // Put Phi operands in UseSet for the incoming edge, not node.
         // They must not "hide" later defs, and must be handled specially
         // during set propagation over the CFG.
-	if (MI->getOpCode() == PHI) {         // for a phi node
+	if (MI->getOpCode() == V9::PHI) {         // for a phi node
           const Value *ArgVal = Op;
 	  const BasicBlock *PredBB = cast<BasicBlock>(*++OpI); // next ptr is BB
 	  
@@ -110,7 +110,7 @@ void BBLiveVar::calcDefUseSets() {
 
     // do for implicit operands as well
     for (unsigned i = 0; i < MI->getNumImplicitRefs(); ++i) {
-      assert(MI->getOpCode() != PHI && "Phi cannot have implicit opeands");
+      assert(MI->getOpCode() != V9::PHI && "Phi cannot have implicit opeands");
       const Value *Op = MI->getImplicitRef(i);
 
       if (Op->getType() == Type::LabelTy)             // don't process labels
diff --git a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
index 3ace61c904..523e21e164 100644
--- a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
+++ b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
@@ -309,7 +309,7 @@ private :
   
   unsigned getOperandMask(unsigned Opcode) {
     switch (Opcode) {
-    case SUBcc:   return 1 << 3;  // Remove CC argument
+    case V9::SUBcc:   return 1 << 3;  // Remove CC argument
   //case BA:      return 1 << 0;  // Remove Arg #0, which is always null or xcc
     default:      return 0;       // By default, don't hack operands...
     }
@@ -320,9 +320,11 @@ inline bool
 SparcFunctionAsmPrinter::OpIsBranchTargetLabel(const MachineInstr *MI,
                                                unsigned int opNum) {
   switch (MI->getOpCode()) {
-  case JMPLCALL:
-  case JMPLRET: return (opNum == 0);
-  default:      return false;
+  case V9::JMPLCALL:
+  case V9::JMPLRET:
+    return (opNum == 0);
+  default:
+    return false;
   }
 }
 
diff --git a/lib/Target/SparcV9/SparcV9InstrInfo.cpp b/lib/Target/SparcV9/SparcV9InstrInfo.cpp
index 331fd4608d..6f3f458205 100644
--- a/lib/Target/SparcV9/SparcV9InstrInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9InstrInfo.cpp
@@ -14,7 +14,6 @@
 #include "llvm/Constants.h"
 #include "llvm/DerivedTypes.h"
 #include <stdlib.h>
-using std::vector;
 
 static const uint32_t MAXLO   = (1 << 10) - 1; // set bits set by %lo(*)
 static const uint32_t MAXSIMM = (1 << 12) - 1; // set bits in simm13 field of OR
@@ -84,7 +83,7 @@ GetConstantValueAsSignedInt(const Value *V, bool &isValidConstant)
 
 static inline void
 CreateSETUWConst(const TargetMachine& target, uint32_t C,
-                 Instruction* dest, vector<MachineInstr*>& mvec,
+                 Instruction* dest, std::vector<MachineInstr*>& mvec,
                  bool isSigned = false)
 {
   MachineInstr *miSETHI = NULL, *miOR = NULL;
@@ -100,7 +99,7 @@ CreateSETUWConst(const TargetMachine& target, uint32_t C,
   // Set the high 22 bits in dest if non-zero and simm13 field of OR not enough
   if (!smallNegValue && (C & ~MAXLO) && C > MAXSIMM)
     {
-      miSETHI = BuildMI(SETHI, 2).addZImm(C).addRegDef(dest);
+      miSETHI = BuildMI(V9::SETHI, 2).addZImm(C).addRegDef(dest);
       miSETHI->setOperandHi32(0);
       mvec.push_back(miSETHI);
     }
@@ -111,14 +110,15 @@ CreateSETUWConst(const TargetMachine& target, uint32_t C,
     {
       if (miSETHI)
         { // unsigned value with high-order bits set using SETHI
-          miOR = BuildMI(OR, 3).addReg(dest).addZImm(C).addRegDef(dest);
+          miOR = BuildMI(V9::OR,3).addReg(dest).addZImm(C).addRegDef(dest);
           miOR->setOperandLo32(1);
         }
       else
         { // unsigned or small signed value that fits in simm13 field of OR
           assert(smallNegValue || (C & ~MAXSIMM) == 0);
-          miOR = BuildMI(OR, 3).addMReg(target.getRegInfo().getZeroRegNum())
-                               .addSImm(sC).addRegDef(dest);
+          miOR = BuildMI(V9::OR, 3).addMReg(target.getRegInfo()
+                                                 .getZeroRegNum())
+            .addSImm(sC).addRegDef(dest);
         }
       mvec.push_back(miOR);
     }
@@ -140,14 +140,14 @@ CreateSETUWConst(const TargetMachine& target, uint32_t C,
 
 static inline void
 CreateSETSWConst(const TargetMachine& target, int32_t C,
-                 Instruction* dest, vector<MachineInstr*>& mvec)
+                 Instruction* dest, std::vector<MachineInstr*>& mvec)
 {
   // Set the low 32 bits of dest
   CreateSETUWConst(target, (uint32_t) C,  dest, mvec, /*isSigned*/true);
 
   // Sign-extend to the high 32 bits if needed
   if (C < 0 && (-C) > (int32_t) MAXSIMM)
-    mvec.push_back(BuildMI(SRA, 3).addReg(dest).addZImm(0).addRegDef(dest));
+    mvec.push_back(BuildMI(V9::SRA, 3).addReg(dest).addZImm(0).addRegDef(dest));
 }
 
 
@@ -164,7 +164,7 @@ CreateSETSWConst(const TargetMachine& target, int32_t C,
 static inline void
 CreateSETXConst(const TargetMachine& target, uint64_t C,
                 Instruction* tmpReg, Instruction* dest,
-                vector<MachineInstr*>& mvec)
+                std::vector<MachineInstr*>& mvec)
 {
   assert(C > (unsigned int) ~0 && "Use SETUW/SETSW for 32-bit values!");
   
@@ -174,13 +174,14 @@ CreateSETXConst(const TargetMachine& target, uint64_t C,
   CreateSETUWConst(target, (C >> 32), tmpReg, mvec);
   
   // Shift tmpReg left by 32 bits
-  mvec.push_back(BuildMI(SLLX, 3).addReg(tmpReg).addZImm(32).addRegDef(tmpReg));
+  mvec.push_back(BuildMI(V9::SLLX, 3).addReg(tmpReg).addZImm(32)
+                 .addRegDef(tmpReg));
   
   // Code to set the low 32 bits of the value in register `dest'
   CreateSETUWConst(target, C, dest, mvec);
   
   // dest = OR(tmpReg, dest)
-  mvec.push_back(BuildMI(OR, 3).addReg(dest).addReg(tmpReg).addRegDef(dest));
+  mvec.push_back(BuildMI(V9::OR,3).addReg(dest).addReg(tmpReg).addRegDef(dest));
 }
 
 
@@ -192,17 +193,17 @@ CreateSETXConst(const TargetMachine& target, uint64_t C,
 
 static inline void
 CreateSETUWLabel(const TargetMachine& target, Value* val,
-                 Instruction* dest, vector<MachineInstr*>& mvec)
+                 Instruction* dest, std::vector<MachineInstr*>& mvec)
 {
   MachineInstr* MI;
   
   // Set the high 22 bits in dest
-  MI = BuildMI(SETHI, 2).addReg(val).addRegDef(dest);
+  MI = BuildMI(V9::SETHI, 2).addReg(val).addRegDef(dest);
   MI->setOperandHi32(0);
   mvec.push_back(MI);
   
   // Set the low 10 bits in dest
-  MI = BuildMI(OR, 3).addReg(dest).addReg(val).addRegDef(dest);
+  MI = BuildMI(V9::OR, 3).addReg(dest).addReg(val).addRegDef(dest);
   MI->setOperandLo32(1);
   mvec.push_back(MI);
 }
@@ -217,30 +218,31 @@ CreateSETUWLabel(const TargetMachine& target, Value* val,
 static inline void
 CreateSETXLabel(const TargetMachine& target,
                 Value* val, Instruction* tmpReg, Instruction* dest,
-                vector<MachineInstr*>& mvec)
+                std::vector<MachineInstr*>& mvec)
 {
   assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
          "I only know about constant values and global addresses");
   
   MachineInstr* MI;
   
-  MI = BuildMI(SETHI, 2).addPCDisp(val).addRegDef(tmpReg);
+  MI = BuildMI(V9::SETHI, 2).addPCDisp(val).addRegDef(tmpReg);
   MI->setOperandHi64(0);
   mvec.push_back(MI);
   
-  MI = BuildMI(OR, 3).addReg(tmpReg).addPCDisp(val).addRegDef(tmpReg);
+  MI = BuildMI(V9::OR, 3).addReg(tmpReg).addPCDisp(val).addRegDef(tmpReg);
   MI->setOperandLo64(1);
   mvec.push_back(MI);
   
-  mvec.push_back(BuildMI(SLLX, 3).addReg(tmpReg).addZImm(32).addRegDef(tmpReg));
-  MI = BuildMI(SETHI, 2).addPCDisp(val).addRegDef(dest);
+  mvec.push_back(BuildMI(V9::SLLX, 3).addReg(tmpReg).addZImm(32)
+                 .addRegDef(tmpReg));
+  MI = BuildMI(V9::SETHI, 2).addPCDisp(val).addRegDef(dest);
   MI->setOperandHi32(0);
   mvec.push_back(MI);
   
-  MI = BuildMI(OR, 3).addReg(dest).addReg(tmpReg).addRegDef(dest);
+  MI = BuildMI(V9::OR, 3).addReg(dest).addReg(tmpReg).addRegDef(dest);
   mvec.push_back(MI);
   
-  MI = BuildMI(OR, 3).addReg(dest).addPCDisp(val).addRegDef(dest);
+  MI = BuildMI(V9::OR, 3).addReg(dest).addPCDisp(val).addRegDef(dest);
   MI->setOperandLo32(1);
   mvec.push_back(MI);
 }
@@ -303,7 +305,7 @@ CreateIntSetInstruction(const TargetMachine& target,
 // Entry == 0 ==> no immediate constant field exists at all.
 // Entry >  0 ==> abs(immediate constant) <= Entry
 // 
-vector<int> MaxConstantsTable(Instruction::OtherOpsEnd);
+std::vector<int> MaxConstantsTable(Instruction::OtherOpsEnd);
 
 static int
 MaxConstantForInstr(unsigned llvmOpCode)
@@ -312,20 +314,20 @@ MaxConstantForInstr(unsigned llvmOpCode)
 
   if (llvmOpCode >= Instruction::BinaryOpsBegin &&
       llvmOpCode <  Instruction::BinaryOpsEnd)
-    modelOpCode = ADD;
+    modelOpCode = V9::ADD;
   else
     switch(llvmOpCode) {
-    case Instruction::Ret:   modelOpCode = JMPLCALL; break;
+    case Instruction::Ret:   modelOpCode = V9::JMPLCALL; break;
 
     case Instruction::Malloc:         
     case Instruction::Alloca:         
     case Instruction::GetElementPtr:  
     case Instruction::PHINode:       
     case Instruction::Cast:
-    case Instruction::Call:  modelOpCode = ADD; break;
+    case Instruction::Call:  modelOpCode = V9::ADD; break;
 
     case Instruction::Shl:
-    case Instruction::Shr:   modelOpCode = SLLX; break;
+    case Instruction::Shr:   modelOpCode = V9::SLLX; break;
 
     default: break;
     };
@@ -363,8 +365,8 @@ InitializeMaxConstantsTable()
 /*ctor*/
 UltraSparcInstrInfo::UltraSparcInstrInfo()
   : TargetInstrInfo(SparcMachineInstrDesc,
-                    /*descSize = */ NUM_TOTAL_OPCODES,
-                    /*numRealOpCodes = */ NUM_REAL_OPCODES)
+                    /*descSize = */ V9::NUM_TOTAL_OPCODES,
+                    /*numRealOpCodes = */ V9::NUM_REAL_OPCODES)
 {
   InitializeMaxConstantsTable();
 }
@@ -405,7 +407,7 @@ UltraSparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
                                            Function* F,
                                            Value* val,
                                            Instruction* dest,
-                                           vector<MachineInstr*>& mvec,
+                                           std::vector<MachineInstr*>& mvec,
                                        MachineCodeForInstruction& mcfi) const
 {
   assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
@@ -512,7 +514,7 @@ UltraSparcInstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
                                         Function* F,
                                         Value* val,
                                         Instruction* dest,
-                                        vector<MachineInstr*>& mvec,
+                                        std::vector<MachineInstr*>& mvec,
                                         MachineCodeForInstruction& mcfi) const
 {
   assert((val->getType()->isIntegral() || isa<PointerType>(val->getType()))
@@ -569,7 +571,7 @@ UltraSparcInstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target,
                                         Function* F,
                                         Value* val,
                                         Instruction* dest,
-                                        vector<MachineInstr*>& mvec,
+                                        std::vector<MachineInstr*>& mvec,
                                         MachineCodeForInstruction& mcfi) const
 {
   const Type* opTy   = val->getType();
@@ -612,7 +614,7 @@ UltraSparcInstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
                                                   Function *F,
                                                   Value* src,
                                                   Instruction* dest,
-                                                  vector<MachineInstr*>& mvec,
+                                               std::vector<MachineInstr*>& mvec,
                                           MachineCodeForInstruction& mcfi) const
 {
   bool loadConstantToReg = false;
@@ -620,47 +622,47 @@ UltraSparcInstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
   const Type* resultType = dest->getType();
   
   MachineOpCode opCode = ChooseAddInstructionByType(resultType);
-  if (opCode == INVALID_OPCODE)
-    {
-      assert(0 && "Unsupported result type in CreateCopyInstructionsByType()");
-      return;
-    }
+  if (opCode == V9::INVALID_OPCODE)
+  {
+    assert(0 && "Unsupported result type in CreateCopyInstructionsByType()");
+    return;
+  }
   
   // if `src' is a constant that doesn't fit in the immed field or if it is
   // a global variable (i.e., a constant address), generate a load
   // instruction instead of an add
   // 
   if (isa<Constant>(src))
-    {
-      unsigned int machineRegNum;
-      int64_t immedValue;
-      MachineOperand::MachineOperandType opType =
-        ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
-                         machineRegNum, immedValue);
+  {
+    unsigned int machineRegNum;
+    int64_t immedValue;
+    MachineOperand::MachineOperandType opType =
+      ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
+                       machineRegNum, immedValue);
       
-      if (opType == MachineOperand::MO_VirtualRegister)
-        loadConstantToReg = true;
-    }
+    if (opType == MachineOperand::MO_VirtualRegister)
+      loadConstantToReg = true;
+  }
   else if (isa<GlobalValue>(src))
     loadConstantToReg = true;
   
   if (loadConstantToReg)
-    { // `src' is constant and cannot fit in immed field for the ADD
-      // Insert instructions to "load" the constant into a register
-      target.getInstrInfo().CreateCodeToLoadConst(target, F, src, dest,
-                                                  mvec, mcfi);
-    }
+  { // `src' is constant and cannot fit in immed field for the ADD
+    // Insert instructions to "load" the constant into a register
+    target.getInstrInfo().CreateCodeToLoadConst(target, F, src, dest,
+                                                mvec, mcfi);
+  }
   else
-    { // Create an add-with-0 instruction of the appropriate type.
-      // Make `src' the second operand, in case it is a constant
-      // Use (unsigned long) 0 for a NULL pointer value.
-      // 
-      const Type* Ty =isa<PointerType>(resultType) ? Type::ULongTy : resultType;
-      MachineInstr* MI =
-        BuildMI(opCode, 3).addReg(Constant::getNullValue(Ty))
-                          .addReg(src).addRegDef(dest);
-      mvec.push_back(MI);
-    }
+  { // Create an add-with-0 instruction of the appropriate type.
+    // Make `src' the second operand, in case it is a constant
+    // Use (unsigned long) 0 for a NULL pointer value.
+    // 
+    const Type* Ty =isa<PointerType>(resultType) ? Type::ULongTy : resultType;
+    MachineInstr* MI =
+      BuildMI(opCode, 3).addReg(Constant::getNullValue(Ty))
+      .addReg(src).addRegDef(dest);
+    mvec.push_back(MI);
+  }
 }
 
 
@@ -673,7 +675,7 @@ CreateBitExtensionInstructions(bool signExtend,
                                Value* srcVal,
                                Value* destVal,
                                unsigned int numLowBits,
-                               vector<MachineInstr*>& mvec,
+                               std::vector<MachineInstr*>& mvec,
                                MachineCodeForInstruction& mcfi)
 {
   MachineInstr* M;
@@ -681,17 +683,17 @@ CreateBitExtensionInstructions(bool signExtend,
   assert(numLowBits <= 32 && "Otherwise, nothing should be done here!");
 
   if (numLowBits < 32)
-    { // SLL is needed since operand size is < 32 bits.
-      TmpInstruction *tmpI = new TmpInstruction(destVal->getType(),
-                                                srcVal, destVal, "make32");
-      mcfi.addTemp(tmpI);
-      mvec.push_back(BuildMI(SLLX, 3).addReg(srcVal).addZImm(32-numLowBits)
-                                     .addRegDef(tmpI));
-      srcVal = tmpI;
-    }
+  { // SLL is needed since operand size is < 32 bits.
+    TmpInstruction *tmpI = new TmpInstruction(destVal->getType(),
+                                              srcVal, destVal, "make32");
+    mcfi.addTemp(tmpI);
+    mvec.push_back(BuildMI(V9::SLLX, 3).addReg(srcVal)
+                   .addZImm(32-numLowBits).addRegDef(tmpI));
+    srcVal = tmpI;
+  }
 
-  mvec.push_back(BuildMI(signExtend? SRA : SRL, 3).addReg(srcVal)
-                         .addZImm(32-numLowBits).addRegDef(destVal));
+  mvec.push_back(BuildMI(signExtend? V9::SRA : V9::SRL, 3)
+                 .addReg(srcVal).addZImm(32-numLowBits).addRegDef(destVal));
 }
 
 
@@ -708,7 +710,7 @@ UltraSparcInstrInfo::CreateSignExtensionInstructions(
                                         Value* srcVal,
                                         Value* destVal,
                                         unsigned int numLowBits,
-                                        vector<MachineInstr*>& mvec,
+                                        std::vector<MachineInstr*>& mvec,
                                         MachineCodeForInstruction& mcfi) const
 {
   CreateBitExtensionInstructions(/*signExtend*/ true, target, F, srcVal,
@@ -730,7 +732,7 @@ UltraSparcInstrInfo::CreateZeroExtensionInstructions(
                                         Value* srcVal,
                                         Value* destVal,
                                         unsigned int numLowBits,
-                                        vector<MachineInstr*>& mvec,
+                                        std::vector<MachineInstr*>& mvec,
                                         MachineCodeForInstruction& mcfi) const
 {
   CreateBitExtensionInstructions(/*signExtend*/ false, target, F, srcVal,
diff --git a/lib/Target/SparcV9/SparcV9InstrSelection.cpp b/lib/Target/SparcV9/SparcV9InstrSelection.cpp
index 78fb2f20d9..1826fbd4cf 100644
--- a/lib/Target/SparcV9/SparcV9InstrSelection.cpp
+++ b/lib/Target/SparcV9/SparcV9InstrSelection.cpp
@@ -270,15 +270,15 @@ ChooseBprInstruction(const InstructionNode* instrNode)
   
   switch(setCCInstr->getOpcode())
     {
-    case Instruction::SetEQ: opCode = BRZ;   break;
-    case Instruction::SetNE: opCode = BRNZ;  break;
-    case Instruction::SetLE: opCode = BRLEZ; break;
-    case Instruction::SetGE: opCode = BRGEZ; break;
-    case Instruction::SetLT: opCode = BRLZ;  break;
-    case Instruction::SetGT: opCode = BRGZ;  break;
+    case Instruction::SetEQ: opCode = V9::BRZ;   break;
+    case Instruction::SetNE: opCode = V9::BRNZ;  break;
+    case Instruction::SetLE: opCode = V9::BRLEZ; break;
+    case Instruction::SetGE: opCode = V9::BRGEZ; break;
+    case Instruction::SetLT: opCode = V9::BRLZ;  break;
+    case Instruction::SetGT: opCode = V9::BRGZ;  break;
     default:
       assert(0 && "Unrecognized VM instruction!");
-      opCode = INVALID_OPCODE;
+      opCode = V9::INVALID_OPCODE;
       break; 
     }
   
@@ -290,7 +290,7 @@ static inline MachineOpCode
 ChooseBpccInstruction(const InstructionNode* instrNode,
                       const BinaryOperator* setCCInstr)
 {
-  MachineOpCode opCode = INVALID_OPCODE;
+  MachineOpCode opCode = V9::INVALID_OPCODE;
   
   bool isSigned = setCCInstr->getOperand(0)->getType()->isSigned();
   
@@ -298,12 +298,12 @@ ChooseBpccInstruction(const InstructionNode* instrNode,
     {
       switch(setCCInstr->getOpcode())
         {
-        case Instruction::SetEQ: opCode = BE;  break;
-        case Instruction::SetNE: opCode = BNE; break;
-        case Instruction::SetLE: opCode = BLE; break;
-        case Instruction::SetGE: opCode = BGE; break;
-        case Instruction::SetLT: opCode = BL;  break;
-        case Instruction::SetGT: opCode = BG;  break;
+        case Instruction::SetEQ: opCode = V9::BE;  break;
+        case Instruction::SetNE: opCode = V9::BNE; break;
+        case Instruction::SetLE: opCode = V9::BLE; break;
+        case Instruction::SetGE: opCode = V9::BGE; break;
+        case Instruction::SetLT: opCode = V9::BL;  break;
+        case Instruction::SetGT: opCode = V9::BG;  break;
         default:
           assert(0 && "Unrecognized VM instruction!");
           break; 
@@ -313,12 +313,12 @@ ChooseBpccInstruction(const InstructionNode* instrNode,
     {
       switch(setCCInstr->getOpcode())
         {
-        case Instruction::SetEQ: opCode = BE;   break;
-        case Instruction::SetNE: opCode = BNE;  break;
-        case Instruction::SetLE: opCode = BLEU; break;
-        case Instruction::SetGE: opCode = BCC;  break;
-        case Instruction::SetLT: opCode = BCS;  break;
-        case Instruction::SetGT: opCode = BGU;  break;
+        case Instruction::SetEQ: opCode = V9::BE;   break;
+        case Instruction::SetNE: opCode = V9::BNE;  break;
+        case Instruction::SetLE: opCode = V9::BLEU; break;
+        case Instruction::SetGE: opCode = V9::BCC;  break;
+        case Instruction::SetLT: opCode = V9::BCS;  break;
+        case Instruction::SetGT: opCode = V9::BGU;  break;
         default:
           assert(0 && "Unrecognized VM instruction!");
           break; 
@@ -332,16 +332,16 @@ static inline MachineOpCode
 ChooseBFpccInstruction(const InstructionNode* instrNode,
                        const BinaryOperator* setCCInstr)
 {
-  MachineOpCode opCode = INVALID_OPCODE;
+  MachineOpCode opCode = V9::INVALID_OPCODE;
   
   switch(setCCInstr->getOpcode())
     {
-    case Instruction::SetEQ: opCode = FBE;  break;
-    case Instruction::SetNE: opCode = FBNE; break;
-    case Instruction::SetLE: opCode = FBLE; break;
-    case Instruction::SetGE: opCode = FBGE; break;
-    case Instruction::SetLT: opCode = FBL;  break;
-    case Instruction::SetGT: opCode = FBG;  break;
+    case Instruction::SetEQ: opCode = V9::FBE;  break;
+    case Instruction::SetNE: opCode = V9::FBNE; break;
+    case Instruction::SetLE: opCode = V9::FBLE; break;
+    case Instruction::SetGE: opCode = V9::FBGE; break;
+    case Instruction::SetLT: opCode = V9::FBL;  break;
+    case Instruction::SetGT: opCode = V9::FBG;  break;
     default:
       assert(0 && "Unrecognized VM instruction!");
       break; 
@@ -405,16 +405,16 @@ ChooseBccInstruction(const InstructionNode* instrNode,
 static inline MachineOpCode 
 ChooseMovFpccInstruction(const InstructionNode* instrNode)
 {
-  MachineOpCode opCode = INVALID_OPCODE;
+  MachineOpCode opCode = V9::INVALID_OPCODE;
   
   switch(instrNode->getInstruction()->getOpcode())
     {
-    case Instruction::SetEQ: opCode = MOVFE;  break;
-    case Instruction::SetNE: opCode = MOVFNE; break;
-    case Instruction::SetLE: opCode = MOVFLE; break;
-    case Instruction::SetGE: opCode = MOVFGE; break;
-    case Instruction::SetLT: opCode = MOVFL;  break;
-    case Instruction::SetGT: opCode = MOVFG;  break;
+    case Instruction::SetEQ: opCode = V9::MOVFE;  break;
+    case Instruction::SetNE: opCode = V9::MOVFNE; break;
+    case Instruction::SetLE: opCode = V9::MOVFLE; break;
+    case Instruction::SetGE: opCode = V9::MOVFGE; break;
+    case Instruction::SetLT: opCode = V9::MOVFL;  break;
+    case Instruction::SetGT: opCode = V9::MOVFG;  break;
     default:
       assert(0 && "Unrecognized VM instruction!");
       break; 
@@ -437,17 +437,17 @@ ChooseMovpccAfterSub(const InstructionNode* instrNode,
                      bool& mustClearReg,
                      int& valueToMove)
 {
-  MachineOpCode opCode = INVALID_OPCODE;
+  MachineOpCode opCode = V9::INVALID_OPCODE;
   mustClearReg = true;
   valueToMove = 1;
   
   switch(instrNode->getInstruction()->getOpcode())
     {
-    case Instruction::SetEQ: opCode = MOVE;  break;
-    case Instruction::SetLE: opCode = MOVLE; break;
-    case Instruction::SetGE: opCode = MOVGE; break;
-    case Instruction::SetLT: opCode = MOVL;  break;
-    case Instruction::SetGT: opCode = MOVG;  break;
+    case Instruction::SetEQ: opCode = V9::MOVE;  break;
+    case Instruction::SetLE: opCode = V9::MOVLE; break;
+    case Instruction::SetGE: opCode = V9::MOVGE; break;
+    case Instruction::SetLT: opCode = V9::MOVL;  break;
+    case Instruction::SetGT: opCode = V9::MOVG;  break;
     case Instruction::SetNE: assert(0 && "No move required!"); break;
     default:		     assert(0 && "Unrecognized VM instr!"); break; 
     }
@@ -458,17 +458,17 @@ ChooseMovpccAfterSub(const InstructionNode* instrNode,
 static inline MachineOpCode
 ChooseConvertToFloatInstr(OpLabel vopCode, const Type* opType)
 {
-  MachineOpCode opCode = INVALID_OPCODE;
+  MachineOpCode opCode = V9::INVALID_OPCODE;
   
   switch(vopCode)
     {
     case ToFloatTy: 
       if (opType == Type::SByteTy || opType == Type::ShortTy || opType == Type::IntTy)
-        opCode = FITOS;
+        opCode = V9::FITOS;
       else if (opType == Type::LongTy)
-        opCode = FXTOS;
+        opCode = V9::FXTOS;
       else if (opType == Type::DoubleTy)
-        opCode = FDTOS;
+        opCode = V9::FDTOS;
       else if (opType == Type::FloatTy)
         ;
       else
@@ -482,11 +482,11 @@ ChooseConvertToFloatInstr(OpLabel vopCode, const Type* opType)
       if (opType == Type::SByteTy || opType == Type::UByteTy ||
           opType == Type::ShortTy || opType == Type::UShortTy ||
           opType == Type::IntTy   || opType == Type::UIntTy)
-        opCode = FITOD;
+        opCode = V9::FITOD;
       else if (opType == Type::LongTy || opType == Type::ULongTy)
-        opCode = FXTOD;
+        opCode = V9::FXTOD;
       else if (opType == Type::FloatTy)
-        opCode = FSTOD;
+        opCode = V9::FSTOD;
       else if (opType == Type::DoubleTy)
         ;
       else
@@ -503,7 +503,7 @@ ChooseConvertToFloatInstr(OpLabel vopCode, const Type* opType)
 static inline MachineOpCode 
 ChooseConvertFPToIntInstr(Type::PrimitiveID tid, const Type* opType)
 {
-  MachineOpCode opCode = INVALID_OPCODE;;
+  MachineOpCode opCode = V9::INVALID_OPCODE;;
 
   assert((opType == Type::FloatTy || opType == Type::DoubleTy)
          && "This function should only be called for FLOAT or DOUBLE");
@@ -516,11 +516,11 @@ ChooseConvertFPToIntInstr(Type::PrimitiveID tid, const Type* opType)
   else if (tid==Type::SByteTyID || tid==Type::ShortTyID || tid==Type::IntTyID ||
            tid==Type::UByteTyID || tid==Type::UShortTyID)
     {
-      opCode = (opType == Type::FloatTy)? FSTOI : FDTOI;
+      opCode = (opType == Type::FloatTy)? V9::FSTOI : V9::FDTOI;
     }
   else if (tid==Type::LongTyID || tid==Type::ULongTyID)
     {
-      opCode = (opType == Type::FloatTy)? FSTOX : FDTOX;
+      opCode = (opType == Type::FloatTy)? V9::FSTOX : V9::FDTOX;
     }
   else
       assert(0 && "Should not get here, Mo!");
@@ -533,7 +533,7 @@ CreateConvertFPToIntInstr(Type::PrimitiveID destTID,
                           Value* srcVal, Value* destVal)
 {
   MachineOpCode opCode = ChooseConvertFPToIntInstr(destTID, srcVal->getType());
-  assert(opCode != INVALID_OPCODE && "Expected to need conversion!");
+  assert(opCode != V9::INVALID_OPCODE && "Expected to need conversion!");
   return BuildMI(opCode, 2).addReg(srcVal).addRegDef(destVal);
 }
 
@@ -594,7 +594,7 @@ static inline MachineInstr*
 CreateMovFloatInstruction(const InstructionNode* instrNode,
                           const Type* resultType)
 {
-  return BuildMI((resultType == Type::FloatTy) ? FMOVS : FMOVD, 2)
+  return BuildMI((resultType == Type::FloatTy) ? V9::FMOVS : V9::FMOVD, 2)
                    .addReg(instrNode->leftChild()->getValue())
                    .addRegDef(instrNode->getValue());
 }
@@ -625,17 +625,17 @@ CreateAddConstInstruction(const InstructionNode* instrNode)
 static inline MachineOpCode 
 ChooseSubInstructionByType(const Type* resultType)
 {
-  MachineOpCode opCode = INVALID_OPCODE;
+  MachineOpCode opCode = V9::INVALID_OPCODE;
   
   if (resultType->isInteger() || isa<PointerType>(resultType))
     {
-      opCode = SUB;
+      opCode = V9::SUB;
     }
   else
     switch(resultType->getPrimitiveID())
       {
-      case Type::FloatTyID:  opCode = FSUBS; break;
-      case Type::DoubleTyID: opCode = FSUBD; break;
+      case Type::FloatTyID:  opCode = V9::FSUBS; break;
+      case Type::DoubleTyID: opCode = V9::FSUBD; break;
       default: assert(0 && "Invalid type for SUB instruction"); break; 
       }
   
@@ -669,12 +669,12 @@ CreateSubConstInstruction(const InstructionNode* instrNode)
 static inline MachineOpCode 
 ChooseFcmpInstruction(const InstructionNode* instrNode)
 {
-  MachineOpCode opCode = INVALID_OPCODE;
+  MachineOpCode opCode = V9::INVALID_OPCODE;
   
   Value* operand = ((InstrTreeNode*) instrNode->leftChild())->getValue();
   switch(operand->getType()->getPrimitiveID()) {
-  case Type::FloatTyID:  opCode = FCMPS; break;
-  case Type::DoubleTyID: opCode = FCMPD; break;
+  case Type::FloatTyID:  opCode = V9::FCMPS; break;
+  case Type::DoubleTyID: opCode = V9::FCMPD; break;
   default: assert(0 && "Invalid type for FCMP instruction"); break; 
   }
   
@@ -703,15 +703,15 @@ BothFloatToDouble(const InstructionNode* instrNode)
 static inline MachineOpCode 
 ChooseMulInstructionByType(const Type* resultType)
 {
-  MachineOpCode opCode = INVALID_OPCODE;
+  MachineOpCode opCode = V9::INVALID_OPCODE;
   
   if (resultType->isInteger())
-    opCode = MULX;
+    opCode = V9::MULX;
   else
     switch(resultType->getPrimitiveID())
       {
-      case Type::FloatTyID:  opCode = FMULS; break;
-      case Type::DoubleTyID: opCode = FMULD; break;
+      case Type::FloatTyID:  opCode = V9::FMULS; break;
+      case Type::DoubleTyID: opCode = V9::FMULD; break;
       default: assert(0 && "Invalid type for MUL instruction"); break; 
       }
   
@@ -724,8 +724,8 @@ static inline MachineInstr*
 CreateIntNegInstruction(const TargetMachine& target,
                         Value* vreg)
 {
-  return BuildMI(SUB, 3).addMReg(target.getRegInfo().getZeroRegNum())
-                        .addReg(vreg).addRegDef(vreg);
+  return BuildMI(V9::SUB, 3).addMReg(target.getRegInfo().getZeroRegNum())
+    .addReg(vreg).addRegDef(vreg);
 }
 
 
@@ -758,7 +758,7 @@ CreateShiftInstructions(const TargetMachine& target,
   // 
   Value* shiftDest = destVal;
   unsigned opSize = target.getTargetData().getTypeSize(argVal1->getType());
-  if ((shiftOpCode == SLL || shiftOpCode == SLLX) && opSize < 8)
+  if ((shiftOpCode == V9::SLL || shiftOpCode == V9::SLLX) && opSize < 8)
     { // put SLL result into a temporary
       shiftDest = new TmpInstruction(argVal1, optArgVal2, "sllTmp");
       mcfi.addTemp(shiftDest);
@@ -792,7 +792,7 @@ CreateMulConstInstruction(const TargetMachine &target, Function* F,
                           MachineCodeForInstruction& mcfi)
 {
   /* Use max. multiply cost, viz., cost of MULX */
-  unsigned cost = target.getInstrInfo().minLatency(MULX);
+  unsigned cost = target.getInstrInfo().minLatency(V9::MULX);
   unsigned firstNewInstr = mvec.size();
   
   Value* constOp = rval;
@@ -805,66 +805,57 @@ CreateMulConstInstruction(const TargetMachine &target, Function* F,
   // 
   const Type* resultType = destVal->getType();
   
-  if (resultType->isInteger() || isa<PointerType>(resultType))
-    {
-      bool isValidConst;
-      int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst);
-      if (isValidConst)
-        {
-          unsigned pow;
-          bool needNeg = false;
-          if (C < 0)
-            {
-              needNeg = true;
-              C = -C;
-            }
+  if (resultType->isInteger() || isa<PointerType>(resultType)) {
+    bool isValidConst;
+    int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst);
+    if (isValidConst) {
+      unsigned pow;
+      bool needNeg = false;
+      if (C < 0) {
+        needNeg = true;
+        C = -C;
+      }
           
-          if (C == 0 || C == 1) {
-            cost = target.getInstrInfo().minLatency(ADD);
-            unsigned Zero = target.getRegInfo().getZeroRegNum();
-            MachineInstr* M;
-            if (C == 0)
-              M = BuildMI(ADD,3).addMReg(Zero).addMReg(Zero).addRegDef(destVal);
-            else
-              M = BuildMI(ADD,3).addReg(lval).addMReg(Zero).addRegDef(destVal);
-            mvec.push_back(M);
-          }
-          else if (isPowerOf2(C, pow))
-            {
-              unsigned opSize = target.getTargetData().getTypeSize(resultType);
-              MachineOpCode opCode = (opSize <= 32)? SLL : SLLX;
-              CreateShiftInstructions(target, F, opCode, lval, NULL, pow,
-                                      destVal, mvec, mcfi); 
-            }
+      if (C == 0 || C == 1) {
+        cost = target.getInstrInfo().minLatency(V9::ADD);
+        unsigned Zero = target.getRegInfo().getZeroRegNum();
+        MachineInstr* M;
+        if (C == 0)
+          M = BuildMI(V9::ADD,3).addMReg(Zero).addMReg(Zero).addRegDef(destVal);
+        else
+          M = BuildMI(V9::ADD,3).addReg(lval).addMReg(Zero).addRegDef(destVal);
+        mvec.push_back(M);
+      }
+      else if (isPowerOf2(C, pow)) {
+        unsigned opSize = target.getTargetData().getTypeSize(resultType);
+        MachineOpCode opCode = (opSize <= 32)? V9::SLL : V9::SLLX;
+        CreateShiftInstructions(target, F, opCode, lval, NULL, pow,
+                                destVal, mvec, mcfi);
+      }
           
-          if (mvec.size() > 0 && needNeg)
-            { // insert <reg = SUB 0, reg> after the instr to flip the sign
-              MachineInstr* M = CreateIntNegInstruction(target, destVal);
-              mvec.push_back(M);
-            }
-        }
+      if (mvec.size() > 0 && needNeg)
+      { // insert <reg = SUB 0, reg> after the instr to flip the sign
+        MachineInstr* M = CreateIntNegInstruction(target, destVal);
+        mvec.push_back(M);
+      }
     }
-  else
-    {
-      if (ConstantFP *FPC = dyn_cast<ConstantFP>(constOp))
-        {
-          double dval = FPC->getValue();