Implement initial prolog/epilog code insertion methods.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11979 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 17 insertions, 6 deletions

diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp
index 7f576f956b..fda45ff3ce 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -13,7 +13,10 @@
 
 #include "SparcV8.h"
 #include "SparcV8RegisterInfo.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/Type.h"
+#include "Support/STLExtras.h"
 using namespace llvm;
 
 SparcV8RegisterInfo::SparcV8RegisterInfo()
@@ -60,18 +63,23 @@ SparcV8RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
   abort();
 }
 
-void SparcV8RegisterInfo::processFunctionBeforeFrameFinalized(
-    MachineFunction &MF) const {
-  abort();
-}
+void SparcV8RegisterInfo::
+processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
 
 void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
-  abort();
+  MachineBasicBlock &MBB = MF.front();
+
+  // Eventually this should emit the correct save instruction based on the
+  // number of bytes in the frame.  For now we just hardcode it.
+  BuildMI(MBB, MBB.begin(), V8::SAVEi, 2, V8::SP).addImm(-122).addReg(V8::SP);
 }
 
 void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
                                        MachineBasicBlock &MBB) const {
-  abort();
+  MachineBasicBlock::iterator MBBI = prior(MBB.end());
+  assert(MBBI->getOpcode() == V8::JMPLi &&
+         "Can only put epilog before return instruction!");
+  BuildMI(MBB, MBBI, V8::RESTOREi, 2, V8::O0).addImm(0).addReg(V8::L7);
 }
 
 
diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td
index 84b4c31602..ccc3be6e44 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.td
+++ b/lib/Target/Sparc/SparcRegisterInfo.td
@@ -26,6 +26,9 @@ let Namespace = "V8" in {
   def I0 : Ri<24>;    def I1 : Ri<25>;    def I2 : Ri<26>;    def I3 : Ri<27>;
   def I4 : Ri<28>;    def I5 : Ri<29>;    def I6 : Ri<30>;    def I7 : Ri<31>;
 
+  // Standard register aliases.
+  def SP : Ri<14>;    def FP : Ri<30>;
+
   // Floating-point registers?
   // ...
 }