Rename the load and store opcodes. The non-fp ones only have one

variant worth worrying about; the fp ones have two.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14362 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 20 insertions, 12 deletions

diff --git a/lib/Target/Sparc/SparcAsmPrinter.cpp b/lib/Target/Sparc/SparcAsmPrinter.cpp
index f8e52472c8..0ef3d84034 100644
--- a/lib/Target/Sparc/SparcAsmPrinter.cpp
+++ b/lib/Target/Sparc/SparcAsmPrinter.cpp
@@ -428,12 +428,16 @@ void V8Printer::printOperand(const MachineInstr *MI, int opNum) {
 
 static bool isLoadInstruction (const MachineInstr *MI) {
   switch (MI->getOpcode ()) {
-  case V8::LDSBmr:
-  case V8::LDSHmr:
-  case V8::LDUBmr:
-  case V8::LDUHmr:
-  case V8::LDmr:
-  case V8::LDDmr:
+  case V8::LDSB:
+  case V8::LDSH:
+  case V8::LDUB:
+  case V8::LDUH:
+  case V8::LD:
+  case V8::LDD:
+  case V8::LDFrr:
+  case V8::LDFri:
+  case V8::LDDFrr:
+  case V8::LDDFri:
     return true;
   default:
     return false;
@@ -442,10 +446,14 @@ static bool isLoadInstruction (const MachineInstr *MI) {
 
 static bool isStoreInstruction (const MachineInstr *MI) {
   switch (MI->getOpcode ()) {
-  case V8::STBrm:
-  case V8::STHrm:
-  case V8::STrm:
-  case V8::STDrm:
+  case V8::STB:
+  case V8::STH:
+  case V8::ST:
+  case V8::STD:
+  case V8::STFrr:
+  case V8::STFri:
+  case V8::STDFrr:
+  case V8::STDFri:
     return true;
   default:
     return false;
diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp
index aa86e4859c..7b8cf0e0c8 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -33,7 +33,7 @@ int SparcV8RegisterInfo::storeRegToStackSlot(
   assert (RC == SparcV8::IntRegsRegisterClass
           && "Can only store 32-bit values to stack slots");
   // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
-  BuildMI (MBB, I, V8::STrm, 3).addFrameIndex (FrameIdx).addSImm (0).addReg (SrcReg);
+  BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0).addReg (SrcReg);
   return 1;
 }
 
@@ -45,7 +45,7 @@ int SparcV8RegisterInfo::loadRegFromStackSlot(
 {
   assert (RC == SparcV8::IntRegsRegisterClass
           && "Can only load 32-bit registers from stack slots");
-  BuildMI (MBB, I, V8::LDmr, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
+  BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
   return 1;
 }