* Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.

* Added a pseudo instruction (for each target) that represent "return void".
  This is a workaround for lack of optional flag operand (return void is not
  lowered so it does not have a flag operand.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24997 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 23 insertions, 14 deletions

diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td
index cccf6f1ad0..79c054eab5 100644
--- a/lib/Target/Sparc/SparcInstrInfo.td
+++ b/lib/Target/Sparc/SparcInstrInfo.td
@@ -93,11 +93,10 @@ def SDT_V8CallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>;
 def callseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_V8CallSeq, [SDNPHasChain]>;
 
-def SDT_V8Call    : SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisVT<1, i32>,
-                                         SDTCisVT<2, FlagVT>]>;
+def SDT_V8Call    : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
 def call          : SDNode<"ISD::CALL", SDT_V8Call, [SDNPHasChain]>;
 
-def SDT_V8RetFlag : SDTypeProfile<0, 1, [ SDTCisVT<0, FlagVT>]>;
+def SDT_V8RetFlag : SDTypeProfile<0, 0, []>;
 def retflag       : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag, [SDNPHasChain]>;
 
 //===----------------------------------------------------------------------===//
@@ -174,8 +173,10 @@ let usesCustomDAGSchedInserter = 1 in {  // Expanded by the scheduler.
 // special cases of JMPL:
 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
   let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
-    def RETL: F3_2<2, 0b111000, (ops),
-                   "retl", [(ret)]>;
+    // FIXME: temporary workaround for return without an incoming flag.
+    def RETVOID: F3_2<2, 0b111000, (ops), "retl", [(ret)]>;
+    let hasInFlag = 1 in
+      def RETL: F3_2<2, 0b111000, (ops), "retl", []>;
 }
 
 // Section B.1 - Load Integer Instructions, p. 90
@@ -559,27 +560,26 @@ def FBO  : FPBranchV8<0b1111, (ops brtarget:$dst),
 
 // Section B.24 - Call and Link Instruction, p. 125
 // This is the only Format 1 instruction
-let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1,
+let Uses = [O0, O1, O2, O3, O4, O5],
+    hasDelaySlot = 1, isCall = 1, hasInFlag = 1, hasOutFlag = 1,
     Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
     D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { 
-  // pc-relative call:
   def CALL : InstV8<(ops calltarget:$dst),
-                    "call $dst",
-                  [(set FLAG, (call tglobaladdr:$dst, FLAG))]> {
+                    "call $dst", []> {
     bits<30> disp;
     let op = 1;
     let Inst{29-0} = disp;
   }
-
+  
   // indirect calls
   def JMPLrr : F3_1<2, 0b111000,
                     (ops MEMrr:$ptr),
                     "call $ptr",
-                    [(set FLAG, (call  ADDRrr:$ptr, FLAG))]>;
+                    [(call  ADDRrr:$ptr)]>;
   def JMPLri : F3_2<2, 0b111000,
                     (ops MEMri:$ptr),
                     "call $ptr",
-                    [(set FLAG, (call  ADDRri:$ptr, FLAG))]>;
+                    [(call  ADDRri:$ptr)]>;
 }
 
 // Section B.28 - Read State Register Instructions
@@ -724,7 +724,15 @@ def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>;
 def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;
 
 // Return of a value, which has an input flag.
-def : Pat<(retflag FLAG), (RETL)>;
+def : Pat<(retflag), (RETL)>;
+
+
+// Calls: 
+def : Pat<(call tglobaladdr:$dst),
+          (CALL tglobaladdr:$dst)>;
+def : Pat<(call externalsym:$dst),
+          (CALL externalsym:$dst)>;
+
 
 // Map integer extload's to zextloads.
 def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp
index 49cbbc091d..f33e5c32e3 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -165,7 +165,8 @@ void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
 void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
                                        MachineBasicBlock &MBB) const {
   MachineBasicBlock::iterator MBBI = prior(MBB.end());
-  assert(MBBI->getOpcode() == V8::RETL &&
+  // FIXME: RETVOID should be removed. See SparcV8InstrInfo.td
+  assert((MBBI->getOpcode() == V8::RETL || MBBI->getOpcode() == V8::RETVOID) &&
          "Can only put epilog before 'retl' instruction!");
   BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
 }