Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30945 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 12 insertions, 13 deletions

diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index c92a19bf7e..299cf06c43 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -436,8 +436,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
       int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
       SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
 
-      OutChains.push_back(DAG.getStore(DAG.getRoot(),
-                                       Arg, FIPtr, DAG.getSrcValue(0)));
+      OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0));
       ArgOffset += 4;
     }
   }
@@ -504,7 +503,7 @@ SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
 
   Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy()));
   
-  SDOperand StackPtr, NullSV;
+  SDOperand StackPtr;
   std::vector<SDOperand> Stores;
   std::vector<SDOperand> RegValuesToPass;
   unsigned ArgOffset = 68;
@@ -584,11 +583,10 @@ SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
     if (ValToStore.Val) {
       if (!StackPtr.Val) {
         StackPtr = DAG.getRegister(SP::O6, MVT::i32);
-        NullSV = DAG.getSrcValue(NULL);
       }
       SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
       PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
-      Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NullSV));
+      Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
     }
     ArgOffset += ObjSize;
   }
@@ -785,8 +783,9 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
     SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
                                    DAG.getRegister(SP::I6, MVT::i32),
                                 DAG.getConstant(VarArgsFrameOffset, MVT::i32));
+    SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
     return DAG.getStore(Op.getOperand(0), Offset, 
-                        Op.getOperand(1), Op.getOperand(2));
+                        Op.getOperand(1), SV->getValue(), SV->getOffset());
   }
   case ISD::VAARG: {
     SDNode *Node = Op.Val;
@@ -802,7 +801,7 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
                                                     getPointerTy()));
     // Store the incremented VAList to the legalized pointer
     InChain = DAG.getStore(VAList.getValue(1), NextPtr,
-                           VAListPtr, Node->getOperand(2));
+                           VAListPtr, SV->getValue(), SV->getOffset());
     // Load the actual argument out of the pointer VAList, unless this is an
     // f64 load.
     if (VT != MVT::f64) {
diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td
index aa7516db44..6b7cddcdcb 100644
--- a/lib/Target/Sparc/SparcInstrInfo.td
+++ b/lib/Target/Sparc/SparcInstrInfo.td
@@ -338,19 +338,19 @@ def LDDFri : F3_2<3, 0b100011,
 def STBrr : F3_1<3, 0b000101,
                  (ops MEMrr:$addr, IntRegs:$src),
                  "stb $src, [$addr]",
-                 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>;
+                 [(truncstorei8 IntRegs:$src, ADDRrr:$addr)]>;
 def STBri : F3_2<3, 0b000101,
                  (ops MEMri:$addr, IntRegs:$src),
                  "stb $src, [$addr]",
-                 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>;
+                 [(truncstorei8 IntRegs:$src, ADDRri:$addr)]>;
 def STHrr : F3_1<3, 0b000110,
                  (ops MEMrr:$addr, IntRegs:$src),
                  "sth $src, [$addr]",
-                 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>;
+                 [(truncstorei16 IntRegs:$src, ADDRrr:$addr)]>;
 def STHri : F3_2<3, 0b000110,
                  (ops MEMri:$addr, IntRegs:$src),
                  "sth $src, [$addr]",
-                 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>;
+                 [(truncstorei16 IntRegs:$src, ADDRri:$addr)]>;
 def STrr  : F3_1<3, 0b000100,
                  (ops MEMrr:$addr, IntRegs:$src),
                  "st $src, [$addr]",
@@ -772,7 +772,7 @@ def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
 
 // truncstore bool -> truncstore byte.
-def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1), 
+def : Pat<(truncstorei1 IntRegs:$src, ADDRrr:$addr),
           (STBrr ADDRrr:$addr, IntRegs:$src)>;
-def : Pat<(truncstore IntRegs:$src, ADDRri:$addr, i1), 
+def : Pat<(truncstorei1 IntRegs:$src, ADDRri:$addr), 
           (STBri ADDRri:$addr, IntRegs:$src)>;