diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2006-10-09 20:57:25 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2006-10-09 20:57:25 +0000 |
| commit | 466685d41a9ea4905b9486fea38e83802e46f196 (patch) | |
| tree | 5cce15f398aa815a729d1e74d62617d58a267bb8 /lib/Target/Sparc/SparcInstrInfo.td | |
| parent | 24446e253a17720f6462288255ab5ebd13b8491f (diff) | |
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30844 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc/SparcInstrInfo.td')
| -rw-r--r-- | lib/Target/Sparc/SparcInstrInfo.td | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index 0137a0d622..6fc4481934 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -278,35 +278,35 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in { def LDSBrr : F3_1<3, 0b001001, (ops IntRegs:$dst, MEMrr:$addr), "ldsb [$addr], $dst", - [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>; + [(set IntRegs:$dst, (sextloadi8 ADDRrr:$addr))]>; def LDSBri : F3_2<3, 0b001001, (ops IntRegs:$dst, MEMri:$addr), "ldsb [$addr], $dst", - [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>; + [(set IntRegs:$dst, (sextloadi8 ADDRri:$addr))]>; def LDSHrr : F3_1<3, 0b001010, (ops IntRegs:$dst, MEMrr:$addr), "ldsh [$addr], $dst", - [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>; + [(set IntRegs:$dst, (sextloadi16 ADDRrr:$addr))]>; def LDSHri : F3_2<3, 0b001010, (ops IntRegs:$dst, MEMri:$addr), "ldsh [$addr], $dst", - [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>; + [(set IntRegs:$dst, (sextloadi16 ADDRri:$addr))]>; def LDUBrr : F3_1<3, 0b000001, (ops IntRegs:$dst, MEMrr:$addr), "ldub [$addr], $dst", - [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>; + [(set IntRegs:$dst, (zextloadi8 ADDRrr:$addr))]>; def LDUBri : F3_2<3, 0b000001, (ops IntRegs:$dst, MEMri:$addr), "ldub [$addr], $dst", - [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>; + [(set IntRegs:$dst, (zextloadi8 ADDRri:$addr))]>; def LDUHrr : F3_1<3, 0b000010, (ops IntRegs:$dst, MEMrr:$addr), "lduh [$addr], $dst", - [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>; + [(set IntRegs:$dst, (zextloadi16 ADDRrr:$addr))]>; def LDUHri : F3_2<3, 0b000010, (ops IntRegs:$dst, MEMri:$addr), "lduh [$addr], $dst", - [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>; + [(set IntRegs:$dst, (zextloadi16 ADDRri:$addr))]>; def LDrr : F3_1<3, 0b000000, (ops IntRegs:$dst, MEMrr:$addr), "ld [$addr], $dst", @@ -760,16 +760,16 @@ def : Pat<(call texternalsym:$dst), def : Pat<(ret), (RETL)>; // Map integer extload's to zextloads. -def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>; -def : Pat<(i32 (extload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>; -def : Pat<(i32 (extload ADDRrr:$src, i8)), (LDUBrr ADDRrr:$src)>; -def : Pat<(i32 (extload ADDRri:$src, i8)), (LDUBri ADDRri:$src)>; -def : Pat<(i32 (extload ADDRrr:$src, i16)), (LDUHrr ADDRrr:$src)>; -def : Pat<(i32 (extload ADDRri:$src, i16)), (LDUHri ADDRri:$src)>; +def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; +def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; +def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; +def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; +def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; +def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; // zextload bool -> zextload byte -def : Pat<(i32 (zextload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>; -def : Pat<(i32 (zextload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>; +def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; +def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; // truncstore bool -> truncstore byte. def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1), |