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authorChristian Konig <christian.koenig@amd.com>2013-03-26 14:03:44 +0000
committerChristian Konig <christian.koenig@amd.com>2013-03-26 14:03:44 +0000
commite981802d9ba81173a300b2c4f79e6576d8f43b7a (patch)
tree618eb940002ca279446d338e18a49ec6f202b4da /lib/Target/R600
parentb78821d380b6f9514bd3b56b1c27ba367660228b (diff)
R600/SI: fix ELSE pseudo op handling
Restore the EXEC mask early, otherwise a copy might end up not beeing executed. Candidate for the mesa stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178018 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600')
-rw-r--r--lib/Target/R600/SILowerControlFlow.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/R600/SILowerControlFlow.cpp b/lib/Target/R600/SILowerControlFlow.cpp
index 9a027e77eb..6b3f6261df 100644
--- a/lib/Target/R600/SILowerControlFlow.cpp
+++ b/lib/Target/R600/SILowerControlFlow.cpp
@@ -197,7 +197,8 @@ void SILowerControlFlowPass::Else(MachineInstr &MI) {
unsigned Dst = MI.getOperand(0).getReg();
unsigned Src = MI.getOperand(1).getReg();
- BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
+ BuildMI(MBB, MBB.getFirstNonPHI(), DL,
+ TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
.addReg(Src); // Saved EXEC
BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)