diff options
author | Christian Konig <christian.koenig@amd.com> | 2013-03-01 09:46:04 +0000 |
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committer | Christian Konig <christian.koenig@amd.com> | 2013-03-01 09:46:04 +0000 |
commit | 9ff8dc8ecd40c6db69778ec4e476a2074facf7e0 (patch) | |
tree | b8294cd0fbd0386a4d03dc509de37c067877bf4f /lib/Target/R600/SIInsertWaits.cpp | |
parent | 4d9b7c234fd2510c27e6d74a3f0653efc0141580 (diff) |
R600/SI: fix inserting waits for unordered defines
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176342 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/SIInsertWaits.cpp')
-rw-r--r-- | lib/Target/R600/SIInsertWaits.cpp | 23 |
1 files changed, 21 insertions, 2 deletions
diff --git a/lib/Target/R600/SIInsertWaits.cpp b/lib/Target/R600/SIInsertWaits.cpp index 24fc929369..67fbdf7be1 100644 --- a/lib/Target/R600/SIInsertWaits.cpp +++ b/lib/Target/R600/SIInsertWaits.cpp @@ -88,6 +88,9 @@ private: MachineBasicBlock::iterator I, const Counters &Counts); + /// \brief Do we need def2def checks? + bool unorderedDefines(MachineInstr &MI); + /// \brief Resolve all operand dependencies to counter requirements Counters handleOperands(MachineInstr &MI); @@ -125,7 +128,7 @@ Counters SIInsertWaits::getHwCounts(MachineInstr &MI) { // Only consider stores or EXP for EXP_CNT Result.Named.EXP = !!(TSFlags & SIInstrFlags::EXP_CNT && - (MI.getOpcode() == AMDGPU::EXP || !MI.getDesc().mayStore())); + (MI.getOpcode() == AMDGPU::EXP || MI.getDesc().mayStore())); // LGKM may uses larger values if (TSFlags & SIInstrFlags::LGKM_CNT) { @@ -299,8 +302,21 @@ static void increaseCounters(Counters &Dst, const Counters &Src) { Dst.Array[i] = std::max(Dst.Array[i], Src.Array[i]); } +bool SIInsertWaits::unorderedDefines(MachineInstr &MI) { + + uint64_t TSFlags = TII->get(MI.getOpcode()).TSFlags; + if (TSFlags & SIInstrFlags::LGKM_CNT) + return true; + + if (TSFlags & SIInstrFlags::EXP_CNT) + return ExpInstrTypesSeen == 3; + + return false; +} + Counters SIInsertWaits::handleOperands(MachineInstr &MI) { + bool UnorderedDefines = unorderedDefines(MI); Counters Result = ZeroCounts; // For each register affected by this @@ -311,8 +327,11 @@ Counters SIInsertWaits::handleOperands(MachineInstr &MI) { RegInterval Interval = getRegInterval(Op); for (unsigned j = Interval.first; j < Interval.second; ++j) { - if (Op.isDef()) + if (Op.isDef()) { increaseCounters(Result, UsedRegs[j]); + if (UnorderedDefines) + increaseCounters(Result, DefinedRegs[j]); + } if (Op.isUse()) increaseCounters(Result, DefinedRegs[j]); |