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authorVincent Lejeune <vljn@ovi.com>2013-02-10 17:57:33 +0000
committerVincent Lejeune <vljn@ovi.com>2013-02-10 17:57:33 +0000
commita311c526ed1da64c450bb8842630f6f80c691eca (patch)
tree79c81ea97861ea13e471ec6852f2187c634a6aab /lib/Target/R600/R600Instructions.td
parent09ed9101c8c7e93c1d814e75ff906bf904778dbb (diff)
Test Commit - Remove some trailing whitespace in R600Instructions.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174839 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/R600Instructions.td')
-rw-r--r--lib/Target/R600/R600Instructions.td12
1 files changed, 6 insertions, 6 deletions
diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td
index 2eab765e8e..591f66d2c1 100644
--- a/lib/Target/R600/R600Instructions.td
+++ b/lib/Target/R600/R600Instructions.td
@@ -70,7 +70,7 @@ class InstFlag<string PM = "printOperand", int Default = 0>
let PrintMethod = PM;
}
-// src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers
+// src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers
def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))> {
let PrintMethod = "printSel";
}
@@ -681,7 +681,7 @@ class ExportBufInst : InstR600ISA<(
let Inst{63-32} = Word1;
}
-let Predicates = [isR600toCayman] in {
+let Predicates = [isR600toCayman] in {
//===----------------------------------------------------------------------===//
// Common Instructions R600, R700, Evergreen, Cayman
@@ -1199,7 +1199,7 @@ let Predicates = [isR700] in {
//===----------------------------------------------------------------------===//
let Predicates = [isEG] in {
-
+
def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;
@@ -1450,7 +1450,7 @@ class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
// This is not really necessary, but there were some GPU hangs that appeared
// to be caused by ALU instructions in the next instruction group that wrote
- // to the $ptr registers of the VTX_READ.
+ // to the $ptr registers of the VTX_READ.
// e.g.
// %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
// %T2_X<def> = MOV %ZERO
@@ -1529,7 +1529,7 @@ defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>;
let Predicates = [isCayman] in {
-let isVector = 1 in {
+let isVector = 1 in {
def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
@@ -1811,7 +1811,7 @@ def : Pat <
// SGE Reverse args
def : Pat <
(selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LE),
- (SGE R600_Reg32:$src1, R600_Reg32:$src0)
+ (SGE R600_Reg32:$src1, R600_Reg32:$src0)
>;
// SETGT_DX10 reverse args