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authorTom Stellard <thomas.stellard@amd.com>2013-01-23 21:39:49 +0000
committerTom Stellard <thomas.stellard@amd.com>2013-01-23 21:39:49 +0000
commit254a83e46c0ffb08c5c77d99f64d6e86db550c6f (patch)
tree75726a515395085c36899f35521ae2d759dc7c0c /lib/Target/R600/R600Instructions.td
parent2a3e0d7e76079289e2b007a15c311c51218f0b89 (diff)
R600: Add a llvm.R600.store.swizzle intrinsics
This intrinsic is translated to ALLOC_EXPORT_WORD1_SWIZ, hence its name. It is used to store vs/fs outputs Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173297 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/R600Instructions.td')
-rw-r--r--lib/Target/R600/R600Instructions.td11
1 files changed, 11 insertions, 0 deletions
diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td
index 3e069da780..04b83bc87b 100644
--- a/lib/Target/R600/R600Instructions.td
+++ b/lib/Target/R600/R600Instructions.td
@@ -599,6 +599,17 @@ multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
(ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase,
0, 1, 2, 3, cf_inst, 0)
>;
+ def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 1),
+ (i32 imm:$type), (i32 imm:$arraybase), (i32 imm)),
+ (ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase,
+ 0, 1, 2, 3, cf_inst, 0)
+ >;
+
+ def : Pat<(int_R600_store_swizzle (v4f32 R600_Reg128:$src), imm:$arraybase,
+ imm:$type),
+ (ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase,
+ 0, 1, 2, 3, cf_inst, 0)
+ >;
}
multiclass SteamOutputExportPattern<Instruction ExportInst,