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| author | Hal Finkel <hfinkel@anl.gov> | 2013-04-12 18:17:38 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-04-12 18:17:38 +0000 |
| commit | 81b2fd5819af2d06011d5a2b031e41527d478ba4 (patch) | |
| tree | e40620791ae98c5d0e1ffd2eb086fed8908064af /lib/Target/PowerPC | |
| parent | 1877dc00e7af5e91651d40ce38e5301912ba0960 (diff) | |
Add a comment about the PPC Interpretation64Bit bit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179391 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC')
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrFormats.td | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index 37e26726f7..36f193be99 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -38,6 +38,11 @@ class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> // Fields used for relation models. string BaseName = ""; + + // For cases where multiple instruction definitions really represent the + // same underlying instruction but with one definition for 64-bit arguments + // and one for 32-bit arguments, this bit breaks the degeneracy between + // the two forms and allows TableGen to generate mapping tables. bit Interpretation64Bit = 0; } |