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authorUlrich Weigand <ulrich.weigand@de.ibm.com>2013-03-19 19:50:30 +0000
committerUlrich Weigand <ulrich.weigand@de.ibm.com>2013-03-19 19:50:30 +0000
commit880d82e3dbf8ae6c2babf5943d524bbe25015eba (patch)
treed40246c46e11f74b4d84c29229f5add04ed3457f /lib/Target/PowerPC
parent58ebc0407891c3752fdea6f4dde28940a75db6d2 (diff)
Fix sub-operand size mismatch in tocentry operands.
The tocentry operand class refers to 64-bit values (it is only used in 64-bit, where iPTR is a 64-bit type), but its sole suboperand is designated as 32-bit type. This causes a mismatch to be detected at compile-time with the TableGen patch I'll check in shortly. To fix this, this commit changes the suboperand to a 64-bit type as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177427 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC')
-rw-r--r--lib/Target/PowerPC/PPCInstr64Bit.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td
index 429a921620..c2fdba13d1 100644
--- a/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -30,7 +30,7 @@ def symbolLo64 : Operand<i64> {
let EncoderMethod = "getLO16Encoding";
}
def tocentry : Operand<iPTR> {
- let MIOperandInfo = (ops i32imm:$imm);
+ let MIOperandInfo = (ops i64imm:$imm);
}
def memrs : Operand<iPTR> { // memri where the immediate is a symbolLo64
let PrintMethod = "printMemRegImm";