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author | Dale Johannesen <dalej@apple.com> | 2008-11-17 18:56:34 +0000 |
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committer | Dale Johannesen <dalej@apple.com> | 2008-11-17 18:56:34 +0000 |
commit | a7647e68a451994c5ae012b6a39e0d8d76d95653 (patch) | |
tree | 81d4f525ad5c3f9ec7a9c76c21e7928c568ae95c /lib/Target/PowerPC/README.txt | |
parent | b8c564f72ef75c775ce473e7b450d5c4da933e89 (diff) |
Move some former testcases (low-probability codegen
optimizations) into this wishlist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59455 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/README.txt')
-rw-r--r-- | lib/Target/PowerPC/README.txt | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/README.txt b/lib/Target/PowerPC/README.txt index e5d4002846..688fb30908 100644 --- a/lib/Target/PowerPC/README.txt +++ b/lib/Target/PowerPC/README.txt @@ -752,3 +752,48 @@ LBB2_1: ; bb The 'mr' could be eliminated to folding the add into the cmp better. //===---------------------------------------------------------------------===// +Codegen for the following (low-probability) case deteriorated considerably +when the correctness fixes for unordered comparisons went in (PR 642, 58871). +It should be possible to recover the code quality described in the comments. + +; RUN: llvm-as < %s | llc -march=ppc32 | grep or | count 3 +; This should produce one 'or' or 'cror' instruction per function. + +; RUN: llvm-as < %s | llc -march=ppc32 | grep mfcr | count 3 +; PR2964 + +define i32 @test(double %x, double %y) nounwind { +entry: + %tmp3 = fcmp ole double %x, %y ; <i1> [#uses=1] + %tmp345 = zext i1 %tmp3 to i32 ; <i32> [#uses=1] + ret i32 %tmp345 +} + +define i32 @test2(double %x, double %y) nounwind { +entry: + %tmp3 = fcmp one double %x, %y ; <i1> [#uses=1] + %tmp345 = zext i1 %tmp3 to i32 ; <i32> [#uses=1] + ret i32 %tmp345 +} + +define i32 @test3(double %x, double %y) nounwind { +entry: + %tmp3 = fcmp ugt double %x, %y ; <i1> [#uses=1] + %tmp34 = zext i1 %tmp3 to i32 ; <i32> [#uses=1] + ret i32 %tmp34 +} +//===----------------------------------------------------------------------===// +; RUN: llvm-as < %s | llc -march=ppc32 | not grep fneg + +; This could generate FSEL with appropriate flags (FSEL is not IEEE-safe, and +; should not be generated except with -enable-finite-only-fp-math or the like). +; With the correctness fixes for PR642 (58871) LowerSELECT_CC would need to +; recognize a more elaborate tree than a simple SETxx. + +define double @test_FNEG_sel(double %A, double %B, double %C) { + %D = sub double -0.000000e+00, %A ; <double> [#uses=1] + %Cond = fcmp ugt double %D, -0.000000e+00 ; <i1> [#uses=1] + %E = select i1 %Cond, double %B, double %C ; <double> [#uses=1] + ret double %E +} + |