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authorDale Johannesen <dalej@apple.com>2008-02-14 23:35:16 +0000
committerDale Johannesen <dalej@apple.com>2008-02-14 23:35:16 +0000
commitdb01c8ba26f288636d3f574a96af3499ee6d2579 (patch)
treedfe018bb9bdd766ec53dd61d3679b1c160f85cd8 /lib/Target/PowerPC/PPCSubtarget.cpp
parent9b03daa2a3a668e4313e0d869bb10aad5b08262a (diff)
Rewrite tblgen handling of subtarget features so
it follows the order of the enum, not alphabetical. The motivation is to make -mattr=+ssse3,+sse41 select SSE41 as it ought to. Added "ignored" enum values of 0 to PPC and SPU to avoid compiler warnings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47143 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCSubtarget.cpp')
-rw-r--r--lib/Target/PowerPC/PPCSubtarget.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCSubtarget.cpp b/lib/Target/PowerPC/PPCSubtarget.cpp
index dff53baa16..030dc7a17c 100644
--- a/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -60,6 +60,7 @@ PPCSubtarget::PPCSubtarget(const TargetMachine &tm, const Module &M,
const std::string &FS, bool is64Bit)
: TM(tm)
, StackAlignment(16)
+ , DarwinDirective(PPC::DIR_NONE)
, IsGigaProcessor(false)
, Has64BitSupport(false)
, Use64BitRegs(false)