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author | Evan Cheng <evan.cheng@apple.com> | 2010-09-28 23:50:49 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2010-09-28 23:50:49 +0000 |
commit | 63d66eed16a6ee4e838f2f7a4c8299def0722c20 (patch) | |
tree | 8f6d45aaa9b70a0694825dabb532e81b91a6622d /lib/Target/PowerPC/PPCScheduleG4Plus.td | |
parent | e48155b25a40e0c1f285ab42b99b2503638d6c0d (diff) |
Add support to model pipeline bypass / forwarding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115005 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCScheduleG4Plus.td')
-rw-r--r-- | lib/Target/PowerPC/PPCScheduleG4Plus.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCScheduleG4Plus.td b/lib/Target/PowerPC/PPCScheduleG4Plus.td index 15056c0cfe..00cac3c7ca 100644 --- a/lib/Target/PowerPC/PPCScheduleG4Plus.td +++ b/lib/Target/PowerPC/PPCScheduleG4Plus.td @@ -15,7 +15,7 @@ def IU3 : FuncUnit; // integer unit 3 (7450 simple) def IU4 : FuncUnit; // integer unit 4 (7450 simple) def G4PlusItineraries : ProcessorItineraries< - [IU1, IU2, IU3, IU4, BPU, SLU, FPU1, VFPU, VIU1, VIU2, VPU], [ + [IU1, IU2, IU3, IU4, BPU, SLU, FPU1, VFPU, VIU1, VIU2, VPU], [], [ InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, InstrItinData<IntDivW , [InstrStage<23, [IU2]>]>, |