diff options
| author | Nate Begeman <natebegeman@mac.com> | 2005-04-15 22:12:16 +0000 |
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2005-04-15 22:12:16 +0000 |
| commit | f8b02949e3d13e9b7cd38e029fcbf3e799366aa7 (patch) | |
| tree | 025797138ecad26749d620e07ea0a4cb7d9755e5 /lib/Target/PowerPC/PPCISelPattern.cpp | |
| parent | da3f2968540b0925aee7bad0bf911883fb2c691b (diff) | |
Make pattern isel default for ppc
Add new ppc beta option related to using condition registers
Make pattern isel control flag (-enable-pattern-isel) global and tristate
0 == off
1 == on
2 == target default
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21309 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelPattern.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelPattern.cpp | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp index 8430970e67..6fe2c4ccbf 100644 --- a/lib/Target/PowerPC/PPCISelPattern.cpp +++ b/lib/Target/PowerPC/PPCISelPattern.cpp @@ -1067,7 +1067,7 @@ unsigned ISel::SelectCC(SDOperand CC, unsigned &Opc) { BuildMI(BB, CompareOpc, 2, Result).addReg(Tmp1).addReg(Tmp2); } } else { -#if 0 + if (PPCCRopts) if (CC.getOpcode() == ISD::AND || CC.getOpcode() == ISD::OR) if (CC.getOperand(0).Val->hasOneUse() && CC.getOperand(1).Val->hasOneUse()) { @@ -1093,7 +1093,6 @@ unsigned ISel::SelectCC(SDOperand CC, unsigned &Opc) { return Result; } } -#endif Opc = PPC::BNE; Tmp1 = SelectExpr(CC); BuildMI(BB, PPC::CMPLWI, 2, Result).addReg(Tmp1).addImm(0); @@ -1127,7 +1126,7 @@ void ISel::SelectBranchCC(SDOperand N) unsigned Opc, CCReg; Select(N.getOperand(0)); //chain CCReg = SelectCC(N.getOperand(1), Opc); - + // Iterate to the next basic block, unless we're already at the end of the ilist<MachineBasicBlock>::iterator It = BB, E = BB->getParent()->end(); if (++It == E) It = BB; |