diff options
| author | Nate Begeman <natebegeman@mac.com> | 2005-04-04 06:52:38 +0000 |
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2005-04-04 06:52:38 +0000 |
| commit | e584668f04723777e5c17292ddf7c1098c94fc71 (patch) | |
| tree | 14d8ab85988e53fa233a69526b048d9ee5a4eebc /lib/Target/PowerPC/PPCISelPattern.cpp | |
| parent | 6e02e6842a13b4dbd5848fc62d76ff24f36b43e8 (diff) | |
Fix i64 return, fix CopyFromReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21076 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelPattern.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelPattern.cpp | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp index 35be0a0725..7066b4069c 100644 --- a/lib/Target/PowerPC/PPCISelPattern.cpp +++ b/lib/Target/PowerPC/PPCISelPattern.cpp @@ -172,8 +172,13 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { // We need to load the argument to a virtual register if we determined above // that we ran out of physical registers of the appropriate type if (needsLoad) { + unsigned SubregOffset = 0; + if (ObjectVT == MVT::i8) SubregOffset = 3; + if (ObjectVT == MVT::i16) SubregOffset = 2; int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); + FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, + DAG.getConstant(SubregOffset, MVT::i32)); argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN); } @@ -933,6 +938,9 @@ unsigned ISel::SelectExpr(SDOperand N) { break; } + if (ISD::CopyFromReg == opcode) + DestType = N.getValue(0).getValueType(); + if (DestType == MVT::f64 || DestType == MVT::f32) if (ISD::LOAD != opcode && ISD::EXTLOAD != opcode && ISD::UNDEF != opcode) return SelectExprFP(N, Result); @@ -1109,9 +1117,12 @@ unsigned ISel::SelectExpr(SDOperand N) { case MVT::i8: case MVT::i16: case MVT::i32: - BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R3).addReg(PPC::R3); - if (Node->getValueType(1) == MVT::i32) - BuildMI(BB, PPC::OR, 2, Result+1).addReg(PPC::R4).addReg(PPC::R4); + if (Node->getValueType(1) == MVT::i32) { + BuildMI(BB, PPC::OR, 2, Result+1).addReg(PPC::R3).addReg(PPC::R3); + BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R4).addReg(PPC::R4); + } else { + BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R3).addReg(PPC::R3); + } break; case MVT::f32: case MVT::f64: |