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authorChris Lattner <sabre@nondot.org>2005-08-10 16:35:46 +0000
committerChris Lattner <sabre@nondot.org>2005-08-10 16:35:46 +0000
commitdf706e3f0c3a7936b3bdb6e36bf20642f467ebae (patch)
treedb626a1a7ea18f57b136efbdd911b5d0cffd77ee /lib/Target/PowerPC/PPCISelPattern.cpp
parent0d7d99fd44bb1eaa0c034d26d50d025a160bdb04 (diff)
Changed the XOR case to use the isOprNot predicate.
Patch by Jim Laskey! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22750 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelPattern.cpp')
-rw-r--r--lib/Target/PowerPC/PPCISelPattern.cpp4
1 files changed, 1 insertions, 3 deletions
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index 49bbeb0a59..479e7f2609 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -1752,9 +1752,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
case ISD::XOR: {
// Check for EQV: xor, (xor a, -1), b
- if (N.getOperand(0).getOpcode() == ISD::XOR &&
- isIntImmediate(N.getOperand(0).getOperand(1), Tmp2) &&
- (signed)Tmp2 == -1) {
+ if (isOprNot(N.getOperand(0))) {
Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1));
BuildMI(BB, PPC::EQV, 2, Result).addReg(Tmp1).addReg(Tmp2);