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| author | Chris Lattner <sabre@nondot.org> | 2005-04-02 05:03:24 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-04-02 05:03:24 +0000 |
| commit | 43fdea070cd54094b5c3b69ce5a25c04d93c91af (patch) | |
| tree | 231f7fd2a551ab418a2e458e40626a1d41d12c0a /lib/Target/PowerPC/PPCISelPattern.cpp | |
| parent | 2c8086f4b9916b2d02842be5e375276023225fba (diff) | |
This target doesn't support fabs/fneg yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21010 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelPattern.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelPattern.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp index a6ebbadf56..751b553357 100644 --- a/lib/Target/PowerPC/PPCISelPattern.cpp +++ b/lib/Target/PowerPC/PPCISelPattern.cpp @@ -53,6 +53,10 @@ namespace { // PowerPC has an i16 but no i8 (or i1) SEXTLOAD setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand); setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand); + + // We don't support these yet. + setOperationAction(ISD::FNEG , MVT::f64 , Expand); + setOperationAction(ISD::FABS , MVT::f64 , Expand); addLegalFPImmediate(+0.0); // Necessary for FSEL addLegalFPImmediate(-0.0); // |